Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 42f5551d authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Split out the PCI driver interface to i915_pci.c 



To reclaim a bit of space from i915_drv.c, we can move the routines that
just hook us into the PCI device tree into i915_pci.c

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466773227-7994-14-git-send-email-chris@chris-wilson.co.uk
parent c2dac868

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror 
i915-y := i915_drv.o \

	  i915_irq.o \

	  i915_params.o \

	  i915_pci.o \

          i915_suspend.o \

	  i915_sysfs.o \

	  intel_csr.o \

drivers/gpu/drm/i915/i915_drv.c

+9 −435
Original line number Diff line number Diff line
@@ -53,387 +53,6 @@ 


static struct drm_driver driver;



#define GEN_DEFAULT_PIPEOFFSETS \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }



#define GEN_CHV_PIPEOFFSETS \

	.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \

			  CHV_PIPE_C_OFFSET }, \

	.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \

			   CHV_TRANSCODER_C_OFFSET, }, \

	.palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \

			     CHV_PALETTE_C_OFFSET }



#define CURSOR_OFFSETS \

	.cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }



#define IVB_CURSOR_OFFSETS \

	.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }



#define BDW_COLORS \

	.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }

#define CHV_COLORS \

	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }



static const struct intel_device_info intel_i830_info = {

	.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_845g_info = {

	.gen = 2, .num_pipes = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_i85x_info = {

	.gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_i865g_info = {

	.gen = 2, .num_pipes = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_i915g_info = {

	.gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};

static const struct intel_device_info intel_i915gm_info = {

	.gen = 3, .is_mobile = 1, .num_pipes = 2,

	.cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};

static const struct intel_device_info intel_i945g_info = {

	.gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};

static const struct intel_device_info intel_i945gm_info = {

	.gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,

	.has_hotplug = 1, .cursor_needs_physical = 1,

	.has_overlay = 1, .overlay_needs_physical = 1,

	.supports_tv = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_i965g_info = {

	.gen = 4, .is_broadwater = 1, .num_pipes = 2,

	.has_hotplug = 1,

	.has_overlay = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_i965gm_info = {

	.gen = 4, .is_crestline = 1, .num_pipes = 2,

	.is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,

	.has_overlay = 1,

	.supports_tv = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_g33_info = {

	.gen = 3, .is_g33 = 1, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_overlay = 1,

	.ring_mask = RENDER_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_g45_info = {

	.gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,

	.has_pipe_cxsr = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_gm45_info = {

	.gen = 4, .is_g4x = 1, .num_pipes = 2,

	.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,

	.has_pipe_cxsr = 1, .has_hotplug = 1,

	.supports_tv = 1,

	.ring_mask = RENDER_RING | BSD_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_pineview_info = {

	.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_overlay = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_ironlake_d_info = {

	.gen = 5, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_ironlake_m_info = {

	.gen = 5, .is_mobile = 1, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING | BSD_RING,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_sandybridge_d_info = {

	.gen = 6, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,

	.has_llc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



static const struct intel_device_info intel_sandybridge_m_info = {

	.gen = 6, .is_mobile = 1, .num_pipes = 2,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.has_fbc = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,

	.has_llc = 1,

	GEN_DEFAULT_PIPEOFFSETS,

	CURSOR_OFFSETS,

};



#define GEN7_FEATURES  \

	.gen = 7, .num_pipes = 3, \

	.need_gfx_hws = 1, .has_hotplug = 1, \

	.has_fbc = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.has_llc = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \

	IVB_CURSOR_OFFSETS



static const struct intel_device_info intel_ivybridge_d_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

};



static const struct intel_device_info intel_ivybridge_m_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

	.is_mobile = 1,

};



static const struct intel_device_info intel_ivybridge_q_info = {

	GEN7_FEATURES,

	.is_ivybridge = 1,

	.num_pipes = 0, /* legal, last one wins */

};



#define VLV_FEATURES  \

	.gen = 7, .num_pipes = 2, \

	.need_gfx_hws = 1, .has_hotplug = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.display_mmio_offset = VLV_DISPLAY_BASE, \

	GEN_DEFAULT_PIPEOFFSETS, \

	CURSOR_OFFSETS



static const struct intel_device_info intel_valleyview_m_info = {

	VLV_FEATURES,

	.is_valleyview = 1,

	.is_mobile = 1,

};



static const struct intel_device_info intel_valleyview_d_info = {

	VLV_FEATURES,

	.is_valleyview = 1,

};



#define HSW_FEATURES  \

	GEN7_FEATURES, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \

	.has_ddi = 1, \

	.has_fpga_dbg = 1



static const struct intel_device_info intel_haswell_d_info = {

	HSW_FEATURES,

	.is_haswell = 1,

};



static const struct intel_device_info intel_haswell_m_info = {

	HSW_FEATURES,

	.is_haswell = 1,

	.is_mobile = 1,

};



#define BDW_FEATURES \

	HSW_FEATURES, \

	BDW_COLORS



static const struct intel_device_info intel_broadwell_d_info = {

	BDW_FEATURES,

	.gen = 8,

	.is_broadwell = 1,

};



static const struct intel_device_info intel_broadwell_m_info = {

	BDW_FEATURES,

	.gen = 8, .is_mobile = 1,

	.is_broadwell = 1,

};



static const struct intel_device_info intel_broadwell_gt3d_info = {

	BDW_FEATURES,

	.gen = 8,

	.is_broadwell = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};



static const struct intel_device_info intel_broadwell_gt3m_info = {

	BDW_FEATURES,

	.gen = 8, .is_mobile = 1,

	.is_broadwell = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};



static const struct intel_device_info intel_cherryview_info = {

	.gen = 8, .num_pipes = 3,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.is_cherryview = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	GEN_CHV_PIPEOFFSETS,

	CURSOR_OFFSETS,

	CHV_COLORS,

};



static const struct intel_device_info intel_skylake_info = {

	BDW_FEATURES,

	.is_skylake = 1,

	.gen = 9,

};



static const struct intel_device_info intel_skylake_gt3_info = {

	BDW_FEATURES,

	.is_skylake = 1,

	.gen = 9,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};



static const struct intel_device_info intel_broxton_info = {

	.is_preliminary = 1,

	.is_broxton = 1,

	.gen = 9,

	.need_gfx_hws = 1, .has_hotplug = 1,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.num_pipes = 3,

	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	.has_pooled_eu = 0,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,

	BDW_COLORS,

};



static const struct intel_device_info intel_kabylake_info = {

	BDW_FEATURES,

	.is_kabylake = 1,

	.gen = 9,

};



static const struct intel_device_info intel_kabylake_gt3_info = {

	BDW_FEATURES,

	.is_kabylake = 1,

	.gen = 9,

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,

};



/*

 * Make sure any device matches here are from most specific to most

 * general.  For example, since the Quanta match is based on the subsystem

 * and subvendor IDs, we need it to come before the more general IVB

 * PCI ID matches, otherwise we'll use the wrong info struct above.

 */

static const struct pci_device_id pciidlist[] = {

	INTEL_I830_IDS(&intel_i830_info),

	INTEL_I845G_IDS(&intel_845g_info),

	INTEL_I85X_IDS(&intel_i85x_info),

	INTEL_I865G_IDS(&intel_i865g_info),

	INTEL_I915G_IDS(&intel_i915g_info),

	INTEL_I915GM_IDS(&intel_i915gm_info),

	INTEL_I945G_IDS(&intel_i945g_info),

	INTEL_I945GM_IDS(&intel_i945gm_info),

	INTEL_I965G_IDS(&intel_i965g_info),

	INTEL_G33_IDS(&intel_g33_info),

	INTEL_I965GM_IDS(&intel_i965gm_info),

	INTEL_GM45_IDS(&intel_gm45_info),

	INTEL_G45_IDS(&intel_g45_info),

	INTEL_PINEVIEW_IDS(&intel_pineview_info),

	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),

	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),

	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),

	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),

	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */

	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),

	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),

	INTEL_HSW_D_IDS(&intel_haswell_d_info),

	INTEL_HSW_M_IDS(&intel_haswell_m_info),

	INTEL_VLV_M_IDS(&intel_valleyview_m_info),

	INTEL_VLV_D_IDS(&intel_valleyview_d_info),

	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),

	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),

	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),

	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),

	INTEL_CHV_IDS(&intel_cherryview_info),

	INTEL_SKL_GT1_IDS(&intel_skylake_info),

	INTEL_SKL_GT2_IDS(&intel_skylake_info),

	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),

	INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),

	INTEL_BXT_IDS(&intel_broxton_info),

	INTEL_KBL_GT1_IDS(&intel_kabylake_info),

	INTEL_KBL_GT2_IDS(&intel_kabylake_info),

	INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),

	INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),

	{0, 0, 0}

};

MODULE_DEVICE_TABLE(pci, pciidlist);



static unsigned int i915_load_fail_count;



bool __i915_inject_load_failure(const char *func, int line)
@@ -1968,8 +1587,7 @@ static void i915_driver_unregister(struct drm_i915_private *dev_priv) 
 *   - allocate initial config memory

 *   - setup the DRM framebuffer with the allocated memory

 */

static int i915_driver_load(struct pci_dev *pdev,

			    const struct pci_device_id *ent)

int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)

{

	struct drm_i915_private *dev_priv;

	int ret;
@@ -2051,18 +1669,14 @@ static int i915_driver_load(struct pci_dev *pdev, 
	return ret;

}



static int i915_driver_unload(struct drm_device *dev)

void i915_driver_unload(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;



	intel_fbdev_fini(dev);



	ret = i915_gem_suspend(dev);

	if (ret) {

		DRM_ERROR("failed to idle hardware: %d\n", ret);

		return ret;

	}

	if (i915_gem_suspend(dev))

		DRM_ERROR("failed to idle hardware; continuing to unload!\n");



	intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -2110,8 +1724,6 @@ static int i915_driver_unload(struct drm_device *dev) 
	intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);



	i915_driver_cleanup_early(dev_priv);



	return 0;

}



static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
@@ -2614,40 +2226,6 @@ int i915_reset(struct drm_i915_private *dev_priv) 
	return ret;

}



static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)

{

	struct intel_device_info *intel_info =

		(struct intel_device_info *) ent->driver_data;



	if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {

		DRM_INFO("This hardware requires preliminary hardware support.\n"

			 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");

		return -ENODEV;

	}



	/* Only bind to function 0 of the device. Early generations

	 * used function 1 as a placeholder for multi-head. This causes

	 * us confusion instead, especially on the systems where both

	 * functions have the same PCI-ID!

	 */

	if (PCI_FUNC(pdev->devfn))

		return -ENODEV;



	if (vga_switcheroo_client_probe_defer(pdev))

		return -EPROBE_DEFER;



	return i915_driver_load(pdev, ent);

}



static void

i915_pci_remove(struct pci_dev *pdev)

{

	struct drm_device *dev = pci_get_drvdata(pdev);



	i915_driver_unload(dev);

	drm_dev_unref(dev);

}



static int i915_pm_suspend(struct device *dev)

{

	struct pci_dev *pdev = to_pci_dev(dev);
@@ -3285,7 +2863,7 @@ static int intel_runtime_resume(struct device *device) 
	return ret;

}



static const struct dev_pm_ops i915_pm_ops = {

const struct dev_pm_ops i915_pm_ops = {

	/*

	 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,

	 * PMSG_RESUME]
@@ -3441,16 +3019,10 @@ static struct drm_driver driver = { 
	.patchlevel = DRIVER_PATCHLEVEL,

};



static struct pci_driver i915_pci_driver = {

	.name = DRIVER_NAME,

	.id_table = pciidlist,

	.probe = i915_pci_probe,

	.remove = i915_pci_remove,

	.driver.pm = &i915_pm_ops,

};



static int __init i915_init(void)

{

	extern struct pci_driver i915_pci_driver;



	/*

	 * Enable KMS by default, unless explicitly overriden by

	 * either the i915.modeset prarameter or by the
@@ -3477,6 +3049,8 @@ static int __init i915_init(void) 


static void __exit i915_exit(void)

{

	extern struct pci_driver i915_pci_driver;



	if (!(driver.driver_features & DRIVER_MODESET))

		return; /* Never loaded a driver. */

drivers/gpu/drm/i915/i915_pci.c

0 → 100644
+461 −0

File added.

Preview size limit exceeded, changes collapsed.