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Commit 42a3f891 authored by Sascha Hauer's avatar Sascha Hauer
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ARM i.MX25: Make timer irq work again 



Since i.MX has SPARSE_IRQ enabled the i.MX25 timer is broken. This
is because the internal irqs now start at an offset of NR_IRQS_LEGACY.
The patch fixed this up, but missed the i.MX25 timer which used a
hardcoded value instead of a define. This patch introduces a define
for the timer irq and uses it.

This is broken since introduced with 3.6-rc1:

| commit 8842a9e2
| Author: Shawn Guo <shawn.guo@linaro.org>
| Date:   Thu Jun 14 11:16:14 2012 +0800
|
|    ARM: imx: enable SPARSE_IRQ for imx platform

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 35495173

arch/arm/mach-imx/clk-imx25.c

+1 −1
Original line number Diff line number Diff line
@@ -241,6 +241,6 @@ int __init mx25_clocks_init(void) 
	clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");

	clk_register_clkdev(clk[iim_ipg], "iim", NULL);



	mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);

	mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);

	return 0;

}

arch/arm/plat-mxc/include/mach/mx25.h

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ 
#define MX25_INT_UART1		(NR_IRQS_LEGACY + 45)

#define MX25_INT_GPIO2		(NR_IRQS_LEGACY + 51)

#define MX25_INT_GPIO1		(NR_IRQS_LEGACY + 52)

#define MX25_INT_GPT1		(NR_IRQS_LEGACY + 54)

#define MX25_INT_FEC		(NR_IRQS_LEGACY + 57)



#define MX25_DMA_REQ_SSI2_RX1	22