Loading arch/arm/boot/dts/qcom/sdxpoorwills-coresight.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,23 @@ reg-names = "csr-base"; coresight-name = "coresight-csr"; qcom,usb-bam-support; qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <1>; }; swao_csr: csr@6b0e000 { compatible = "qcom,coresight-csr"; reg = <0x6b0e000 0x1000>; reg-names = "csr-base"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,blk-size = <1>; }; Loading @@ -34,6 +51,7 @@ coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti8>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -93,6 +111,7 @@ coresight-name = "coresight-tmc-etf"; coresight-ctis = <&cti0 &cti8>; coresight-csr = <&csr>; arm,default-sink; clocks = <&clock_aop QDSS_CLK>; Loading Loading @@ -1063,6 +1082,7 @@ "ddr-ch23-ctrl"; coresight-name = "coresight-hwevent"; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills-coresight.dtsi +20 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,23 @@ reg-names = "csr-base"; coresight-name = "coresight-csr"; qcom,usb-bam-support; qcom,hwctrl-set-support; qcom,set-byte-cntr-support; qcom,blk-size = <1>; }; swao_csr: csr@6b0e000 { compatible = "qcom,coresight-csr"; reg = <0x6b0e000 0x1000>; reg-names = "csr-base"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; coresight-name = "coresight-swao-csr"; qcom,timestamp-support; qcom,blk-size = <1>; }; Loading @@ -34,6 +51,7 @@ coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti8>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -93,6 +111,7 @@ coresight-name = "coresight-tmc-etf"; coresight-ctis = <&cti0 &cti8>; coresight-csr = <&csr>; arm,default-sink; clocks = <&clock_aop QDSS_CLK>; Loading Loading @@ -1063,6 +1082,7 @@ "ddr-ch23-ctrl"; coresight-name = "coresight-hwevent"; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; Loading