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Commit 425b655c authored by Thomas Gleixner's avatar Thomas Gleixner
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Merge tag 'irqchip-core-4.1-2' of git://git.infradead.org/users/jcooper/linux into irq/core

irqchip core changes for v4.1 (round 2) from Jason Cooper

 - gic
    - Tolerate uni-processor systems better in gic_get_cpumask()

 - mvebu
    - Handle per-cpu interrupts properly
    - Enable PMU interrupts
    - Enable wakeup source

 - vybrid
    - Add MSCM interrupt router

 - renesas
    - Add PM and wakeup support
parents fdb7144b 78223354
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Freescale Vybrid Miscellaneous System Control - CPU Configuration

The MSCM IP contains multiple sub modules, this binding describes the first
block of registers which contains CPU configuration information.

Required properties:
- compatible:	"fsl,vf610-mscm-cpucfg", "syscon"
- reg:		the register range of the MSCM CPU configuration registers

Example:
	mscm_cpucfg: cpucfg@40001000 {
		compatible = "fsl,vf610-mscm-cpucfg", "syscon";
		reg = <0x40001000 0x800>;
	}
+33 −0
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Freescale Vybrid Miscellaneous System Control - Interrupt Router

The MSCM IP contains multiple sub modules, this binding describes the second
block of registers which control the interrupt router. The interrupt router
allows to configure the recipient of each peripheral interrupt. Furthermore
it controls the directed processor interrupts. The module is available in all
Vybrid SoC's but is only really useful in dual core configurations (VF6xx
which comes with a Cortex-A5/Cortex-M4 combination).

Required properties:
- compatible:		"fsl,vf610-mscm-ir"
- reg:			the register range of the MSCM Interrupt Router
- fsl,cpucfg:		The handle to the MSCM CPU configuration node, required
			to get the current CPU ID
- interrupt-controller:	Identifies the node as an interrupt controller
- #interrupt-cells:	Two cells, interrupt number and cells.
			The hardware interrupt number according to interrupt
			assignment of the interrupt router is required.
			Flags get passed only when using GIC as parent. Flags
			encoding as documented by the GIC bindings.
- interrupt-parent:	Should be the phandle for the interrupt controller of
			the CPU the device tree is intended to be used on. This
			is either the node of the GIC or NVIC controller.

Example:
	mscm_ir: interrupt-controller@40001800 {
		compatible = "fsl,vf610-mscm-ir";
		reg = <0x40001800 0x400>;
		fsl,cpucfg = <&mscm_cpucfg>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
	}
+3 −1
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@@ -4,7 +4,7 @@ Required properties:

- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
  Examples with soctypes are:
    - "renesas,irqc-r8a73a4" (R-Mobile AP6)
    - "renesas,irqc-r8a73a4" (R-Mobile APE6)
    - "renesas,irqc-r8a7790" (R-Car H2)
    - "renesas,irqc-r8a7791" (R-Car M2-W)
    - "renesas,irqc-r8a7792" (R-Car V2H)
@@ -12,6 +12,7 @@ Required properties:
    - "renesas,irqc-r8a7794" (R-Car E2)
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
  interrupts.txt in this directory
- clocks: Must contain a reference to the functional clock.

Optional properties:

@@ -29,4 +30,5 @@ Example:
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
	};
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@@ -631,6 +631,7 @@ config SOC_IMX6SX

config SOC_VF610
	bool "Vybrid Family VF610 support"
	select IRQ_DOMAIN_HIERARCHY
	select ARM_GIC
	select PINCTRL_VF610
	select PL310_ERRATA_769419 if CACHE_L2X0
+1 −0
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@@ -38,6 +38,7 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
obj-$(CONFIG_XTENSA)			+= irq-xtensa-pic.o
obj-$(CONFIG_XTENSA_MX)			+= irq-xtensa-mx.o
obj-$(CONFIG_IRQ_CROSSBAR)		+= irq-crossbar.o
obj-$(CONFIG_SOC_VF610)			+= irq-vf610-mscm-ir.o
obj-$(CONFIG_BCM7120_L2_IRQ)		+= irq-bcm7120-l2.o
obj-$(CONFIG_BRCMSTB_L2_IRQ)		+= irq-brcmstb-l2.o
obj-$(CONFIG_KEYSTONE_IRQ)		+= irq-keystone.o
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