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Commit 41450b1b authored by Takashi Iwai's avatar Takashi Iwai
Browse files

Merge branch 'for-linus' into for-next

parents fe14f39e 6ac7ada2

Documentation/devicetree/bindings/dma/apm-xgene-dma.txt

+1 −1
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@@ -35,7 +35,7 @@ Example: 
			device_type = "dma";

			reg = <0x0 0x1f270000 0x0 0x10000>,

			      <0x0 0x1f200000 0x0 0x10000>,

			      <0x0 0x1b008000 0x0 0x2000>,

			      <0x0 0x1b000000 0x0 0x400000>,

			      <0x0 0x1054a000 0x0 0x100>;

			interrupts = <0x0 0x82 0x4>,

				     <0x0 0xb8 0x4>,

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

+3 −0
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@@ -35,3 +35,6 @@ the PCIe specification. 


                      NOTE: this only applies to the SMMU itself, not

                      masters connected upstream of the SMMU.



- hisilicon,broken-prefetch-cmd

                    : Avoid sending CMD_PREFETCH_* commands to the SMMU.

Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt

+0 −2
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ Required properties: 
	       "fsl,imx6sx-usdhc"



Optional properties:

- fsl,cd-controller : Indicate to use controller internal card detection

- fsl,wp-controller : Indicate to use controller internal write protection

- fsl,delay-line : Specify the number of delay cells for override mode.

  This is used to set the clock delay for DLL(Delay Line) on override mode
@@ -35,7 +34,6 @@ esdhc@70004000 { 
	compatible = "fsl,imx51-esdhc";

	reg = <0x70004000 0x4000>;

	interrupts = <1>;

	fsl,cd-controller;

	fsl,wp-controller;

};

Documentation/devicetree/bindings/spi/spi-ath79.txt

+3 −3
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@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller 
Required properties:

- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.

- reg: Base address and size of the controllers memory area

- clocks: phandle to the AHB clock.

- clocks: phandle of the AHB clock.

- clock-names: has to be "ahb".

- #address-cells: <1>, as required by generic SPI binding.

- #size-cells: <0>, also as required by generic SPI binding.
@@ -12,9 +12,9 @@ Child nodes as per the generic SPI binding. 


Example:



	spi@1F000000 {

	spi@1f000000 {

		compatible = "qca,ar9132-spi", "qca,ar7100-spi";

		reg = <0x1F000000 0x10>;

		reg = <0x1f000000 0x10>;



		clocks = <&pll 2>;

		clock-names = "ahb";

Documentation/hwmon/nct7904

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@@ -35,11 +35,11 @@ temp1_input Local temperature (1/1000 degree, 
temp[2-9]_input		CPU temperatures (1/1000 degree,

			0.125 degree resolution)



fan[1-4]_mode		R/W, 0/1 for manual or SmartFan mode

pwm[1-4]_enable		R/W, 1/2 for manual or SmartFan mode

			Setting SmartFan mode is supported only if it has been

			previously configured by BIOS (or configuration EEPROM)



fan[1-4]_pwm		R/O in SmartFan mode, R/W in manual control mode

pwm[1-4]		R/O in SmartFan mode, R/W in manual control mode



The driver checks sensor control registers and does not export the sensors

that are not enabled. Anyway, a sensor that is enabled may actually be not