Merge "ARM: dts: msm: Add PDC interrupt controller for sdm845" into msm-4.9 (4084be9c) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi

+38 −38

Original line number	Diff line number	Diff line
		@@ -39,44 +39,44 @@
		36 37>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;
		interrupt-map = <0 0 0 0 &intc 0 141 0
		0 0 0 1 &intc 0 149 0
		0 0 0 2 &intc 0 150 0
		0 0 0 3 &intc 0 151 0
		0 0 0 4 &intc 0 152 0
		0 0 0 5 &intc 0 140 0
		0 0 0 6 &intc 0 672 0
		0 0 0 7 &intc 0 673 0
		0 0 0 8 &intc 0 674 0
		0 0 0 9 &intc 0 675 0
		0 0 0 10 &intc 0 676 0
		0 0 0 11 &intc 0 677 0
		0 0 0 12 &intc 0 678 0
		0 0 0 13 &intc 0 679 0
		0 0 0 14 &intc 0 680 0
		0 0 0 15 &intc 0 681 0
		0 0 0 16 &intc 0 682 0
		0 0 0 17 &intc 0 683 0
		0 0 0 18 &intc 0 684 0
		0 0 0 19 &intc 0 685 0
		0 0 0 20 &intc 0 686 0
		0 0 0 21 &intc 0 687 0
		0 0 0 22 &intc 0 688 0
		0 0 0 23 &intc 0 689 0
		0 0 0 24 &intc 0 690 0
		0 0 0 25 &intc 0 691 0
		0 0 0 26 &intc 0 692 0
		0 0 0 27 &intc 0 693 0
		0 0 0 28 &intc 0 694 0
		0 0 0 29 &intc 0 695 0
		0 0 0 30 &intc 0 696 0
		0 0 0 31 &intc 0 697 0
		0 0 0 32 &intc 0 698 0
		0 0 0 33 &intc 0 699 0
		0 0 0 34 &intc 0 700 0
		0 0 0 35 &intc 0 701 0
		0 0 0 36 &intc 0 702 0
		0 0 0 37 &intc 0 703 0>;
		interrupt-map = <0 0 0 0 &pdc 0 141 0
		0 0 0 1 &pdc 0 149 0
		0 0 0 2 &pdc 0 150 0
		0 0 0 3 &pdc 0 151 0
		0 0 0 4 &pdc 0 152 0
		0 0 0 5 &pdc 0 140 0
		0 0 0 6 &pdc 0 672 0
		0 0 0 7 &pdc 0 673 0
		0 0 0 8 &pdc 0 674 0
		0 0 0 9 &pdc 0 675 0
		0 0 0 10 &pdc 0 676 0
		0 0 0 11 &pdc 0 677 0
		0 0 0 12 &pdc 0 678 0
		0 0 0 13 &pdc 0 679 0
		0 0 0 14 &pdc 0 680 0
		0 0 0 15 &pdc 0 681 0
		0 0 0 16 &pdc 0 682 0
		0 0 0 17 &pdc 0 683 0
		0 0 0 18 &pdc 0 684 0
		0 0 0 19 &pdc 0 685 0
		0 0 0 20 &pdc 0 686 0
		0 0 0 21 &pdc 0 687 0
		0 0 0 22 &pdc 0 688 0
		0 0 0 23 &pdc 0 689 0
		0 0 0 24 &pdc 0 690 0
		0 0 0 25 &pdc 0 691 0
		0 0 0 26 &pdc 0 692 0
		0 0 0 27 &pdc 0 693 0
		0 0 0 28 &pdc 0 694 0
		0 0 0 29 &pdc 0 695 0
		0 0 0 30 &pdc 0 696 0
		0 0 0 31 &pdc 0 697 0
		0 0 0 32 &pdc 0 698 0
		0 0 0 33 &pdc 0 699 0
		0 0 0 34 &pdc 0 700 0
		0 0 0 35 &pdc 0 701 0
		0 0 0 36 &pdc 0 702 0
		0 0 0 37 &pdc 0 703 0>;

		interrupt-names = "int_msi", "int_a", "int_b", "int_c",
		"int_d", "int_global_int",

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupt-parent = <&pdc>;

		ufs_dev_reset_assert: ufs_dev_reset_assert {
		config {

arch/arm64/boot/dts/qcom/sdm845-pm.dtsi

+8 −0

Original line number	Diff line number	Diff line
		@@ -145,4 +145,12 @@
		reg = <0xC300000 0x1000>, <0xC3F0004 0x4>;
		reg-names = "phys_addr_base", "offset_addr";
		};

		pdc: interrupt-controller@0xb220000{
		compatible = "qcom,pdc-sdm845";
		reg = <0xb220000 0x400>;
		#interrupt-cells = <3>;
		interrupt-parent = <&intc>;
		interrupt-controller;
		};
		};

arch/arm64/boot/dts/qcom/sdm845-qupv3.dtsi

+2 −2

Original line number	Diff line number	Diff line
		@@ -42,7 +42,7 @@
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_4uart_active>;
		pinctrl-1 = <&qupv3_se6_4uart_sleep>;
		interrupts-extended = <&intc GIC_SPI 607 0>,
		interrupts-extended = <&pdc GIC_SPI 607 0>,
		<&tlmm 48 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		@@ -60,7 +60,7 @@
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_4uart_active>;
		pinctrl-1 = <&qupv3_se7_4uart_sleep>;
		interrupts-extended = <&intc GIC_SPI 608 0>,
		interrupts-extended = <&pdc GIC_SPI 608 0>,
		<&tlmm 96 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -35,7 +35,7 @@
		sde-vdd-supply = <&mdss_core_gdsc>;

		/* interrupt config */
		interrupt-parent = <&intc>;
		interrupt-parent = <&pdc>;
		interrupts = <0 83 0>;
		interrupt-controller;
		#interrupt-cells = <1>;