Loading Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt 0 → 100644 +733 −0 Original line number Diff line number Diff line Device tree binding for NVIDIA Tegra XUSB pad controller ======================================================== The Tegra XUSB pad controller manages a set of I/O lanes (with differential signals) which connect directly to pins/pads on the SoC package. Each lane is controlled by a HW block referred to as a "pad" in the Tegra hardware documentation. Each such "pad" may control either one or multiple lanes, and thus contains any logic common to all its lanes. Each lane can be separately configured and powered up. Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or super-speed USB. Other lanes are for various types of low-speed, full-speed or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller contains a software-configurable mux that sits between the I/O controller ports (e.g. PCIe) and the lanes. In addition to per-lane configuration, USB 3.0 ports may require additional settings on a per-board basis. Pads will be represented as children of the top-level XUSB pad controller device tree node. Each lane exposed by the pad will be represented by its own subnode and can be referenced by users of the lane using the standard PHY bindings, as described by the phy-bindings.txt file in this directory. The Tegra hardware documentation refers to the connection between the XUSB pad controller and the XUSB controller as "ports". This is confusing since "port" is typically used to denote the physical USB receptacle. The device tree binding in this document uses the term "port" to refer to the logical abstraction of the signals that are routed to a USB receptacle (i.e. a PHY for the USB signal, the VBUS power supply, the USB 2.0 companion port for USB 3.0 receptacles, ...). Required properties: -------------------- - compatible: Must be: - Tegra124: "nvidia,tegra124-xusb-padctl" - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: - "padctl" Pad nodes: ========== A required child node named "pads" contains a list of subnodes, one for each of the pads exposed by the XUSB pad controller. Each pad may need additional resources that can be referenced in its pad node. The "status" property is used to enable or disable the use of a pad. If set to "disabled", the pad will not be used on the given board. In order to use the pad and any of its lanes, this property must be set to "okay". For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie and sata. No extra resources are required for operation of these pads. For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is a description of the properties of each pad. UTMI pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "trk": phandle and specifier referring to the USB2 tracking clock HSIC pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "trk": phandle and specifier referring to the HSIC tracking clock PCIe pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "pll": phandle and specifier referring to the PLLE - resets: Must contain an entry for each entry in reset-names. - reset-names: Must contain the following entries: - "phy": reset for the PCIe UPHY block SATA pad: --------- Required properties: - resets: Must contain an entry for each entry in reset-names. - reset-names: Must contain the following entries: - "phy": reset for the SATA UPHY block PHY nodes: ========== Each pad node has a child named "lanes" that contains one or more children of its own, each representing one of the lanes controlled by the pad. Required properties: -------------------- - status: Defines the operation status of the PHY. Valid values are: - "disabled": the PHY is disabled - "okay": the PHY is enabled - #phy-cells: Should be 0. Since each lane represents a single PHY, there is no need for an additional specifier. - nvidia,function: The output function of the PHY. See below for a list of valid functions per SoC generation. For Tegra124 and Tegra132, the list of valid PHY nodes is given below: - usb2: usb2-0, usb2-1, usb2-2 - functions: "snps", "xusb", "uart" - ulpi: ulpi-0 - functions: "snps", "xusb" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4 - functions: "pcie", "usb3-ss" - sata: sata-0 - functions: "usb3-ss", "sata" For Tegra210, the list of valid PHY nodes is given below: - utmi: utmi-0, utmi-1, utmi-2, utmi-3 - functions: "snps", "xusb", "uart" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 - functions: "pcie-x1", "usb3-ss", "pcie-x4" - sata: sata-0 - functions: "usb3-ss", "sata" Port nodes: =========== A required child node named "ports" contains a list of all the ports exposed by the XUSB pad controller. Per-port configuration is only required for USB. USB2 ports: ----------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - mode: A string that determines the mode in which to run the port. Valid values are: - "host": for USB host mode - "device": for USB device mode - "otg": for USB OTG mode Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. - vbus-supply: phandle to a regulator supplying the VBUS voltage. ULPI ports: ----------- Optional properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. - vbus-supply: phandle to a regulator supplying the VBUS voltage. HSIC ports: ----------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled Optional properties: - vbus-supply: phandle to a regulator supplying the VBUS voltage. Super-speed USB ports: ---------------------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - nvidia,usb2-companion: A single cell that specifies the physical port number to map this super-speed USB port to. The range of valid port numbers varies with the SoC generation: - 0-2: for Tegra124 and Tegra132 - 0-3: for Tegra210 Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 - 1x ULPI: ulpi-0 - 2x HSIC: hsic-0, hsic-1 - 2x super-speed USB: usb3-0, usb3-1 For Tegra210, the XUSB pad controller exposes the following ports: - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: ========= Tegra124 and Tegra132: ---------------------- SoC include: padctl@7009f000 { /* for Tegra124 */ compatible = "nvidia,tegra124-xusb-padctl"; /* for Tegra132 */ compatible = "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; pads { usb2 { status = "disabled"; lanes { usb2-0 { status = "disabled"; #phy-cells = <0>; }; usb2-1 { status = "disabled"; #phy-cells = <0>; }; usb2-2 { status = "disabled"; #phy-cells = <0>; }; }; }; ulpi { status = "disabled"; lanes { ulpi-0 { status = "disabled"; #phy-cells = <0>; }; }; }; hsic { status = "disabled"; lanes { hsic-0 { status = "disabled"; #phy-cells = <0>; }; hsic-1 { status = "disabled"; #phy-cells = <0>; }; }; }; pcie { status = "disabled"; lanes { pcie-0 { status = "disabled"; #phy-cells = <0>; }; pcie-1 { status = "disabled"; #phy-cells = <0>; }; pcie-2 { status = "disabled"; #phy-cells = <0>; }; pcie-3 { status = "disabled"; #phy-cells = <0>; }; pcie-4 { status = "disabled"; #phy-cells = <0>; }; }; }; sata { status = "disabled"; lanes { sata-0 { status = "disabled"; #phy-cells = <0>; }; }; }; }; ports { usb2-0 { status = "disabled"; }; usb2-1 { status = "disabled"; }; usb2-2 { status = "disabled"; }; ulpi-0 { status = "disabled"; }; hsic-0 { status = "disabled"; }; hsic-1 { status = "disabled"; }; usb3-0 { status = "disabled"; }; usb3-1 { status = "disabled"; }; }; }; Board file: padctl@7009f000 { status = "okay"; pads { usb2 { status = "okay"; lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; usb2-1 { nvidia,function = "xusb"; status = "okay"; }; usb2-2 { nvidia,function = "xusb"; status = "okay"; }; }; }; pcie { status = "okay"; lanes { pcie-0 { nvidia,function = "usb3-ss"; status = "okay"; }; pcie-2 { nvidia,function = "pcie"; status = "okay"; }; pcie-4 { nvidia,function = "pcie"; status = "okay"; }; }; }; sata { status = "okay"; lanes { sata-0 { nvidia,function = "sata"; status = "okay"; }; }; }; }; ports { /* Micro A/B */ usb2-0 { status = "okay"; mode = "otg"; }; /* Mini PCIe */ usb2-1 { status = "okay"; mode = "host"; }; /* USB3 */ usb2-2 { status = "okay"; mode = "host"; vbus-supply = <&vdd_usb3_vbus>; }; usb3-0 { nvidia,port = <2>; status = "okay"; }; }; }; Tegra210: --------- SoC include: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; status = "disabled"; pads { usb2 { clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; clock-names = "trk"; status = "disabled"; lanes { usb2-0 { status = "disabled"; #phy-cells = <0>; }; usb2-1 { status = "disabled"; #phy-cells = <0>; }; usb2-2 { status = "disabled"; #phy-cells = <0>; }; usb2-3 { status = "disabled"; #phy-cells = <0>; }; }; }; hsic { clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; clock-names = "trk"; status = "disabled"; lanes { hsic-0 { status = "disabled"; #phy-cells = <0>; }; hsic-1 { status = "disabled"; #phy-cells = <0>; }; }; }; pcie { clocks = <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "pll"; resets = <&tegra_car 205>; reset-names = "phy"; status = "disabled"; lanes { pcie-0 { status = "disabled"; #phy-cells = <0>; }; pcie-1 { status = "disabled"; #phy-cells = <0>; }; pcie-2 { status = "disabled"; #phy-cells = <0>; }; pcie-3 { status = "disabled"; #phy-cells = <0>; }; pcie-4 { status = "disabled"; #phy-cells = <0>; }; pcie-5 { status = "disabled"; #phy-cells = <0>; }; pcie-6 { status = "disabled"; #phy-cells = <0>; }; }; }; sata { clocks = <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "pll"; resets = <&tegra_car 204>; reset-names = "phy"; status = "disabled"; lanes { sata-0 { status = "disabled"; #phy-cells = <0>; }; }; }; }; ports { usb2-0 { status = "disabled"; }; usb2-1 { status = "disabled"; }; usb2-2 { status = "disabled"; }; usb2-3 { status = "disabled"; }; hsic-0 { status = "disabled"; }; hsic-1 { status = "disabled"; }; usb3-0 { status = "disabled"; }; usb3-1 { status = "disabled"; }; usb3-2 { status = "disabled"; }; usb3-3 { status = "disabled"; }; }; }; Board file: padctl@7009f000 { status = "okay"; pads { usb2 { status = "okay"; lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; usb2-1 { nvidia,function = "xusb"; status = "okay"; }; usb2-2 { nvidia,function = "xusb"; status = "okay"; }; usb2-3 { nvidia,function = "xusb"; status = "okay"; }; }; }; pcie { status = "okay"; lanes { pcie-0 { nvidia,function = "pcie-x1"; status = "okay"; }; pcie-1 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-2 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-3 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-4 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-5 { nvidia,function = "usb3-ss"; status = "okay"; }; pcie-6 { nvidia,function = "usb3-ss"; status = "okay"; }; }; }; sata { status = "okay"; lanes { sata-0 { nvidia,function = "sata"; status = "okay"; }; }; }; }; ports { usb2-0 { status = "okay"; mode = "otg"; }; usb2-1 { status = "okay"; vbus-supply = <&vdd_5v0_rtl>; mode = "host"; }; usb2-2 { status = "okay"; vbus-supply = <&vdd_usb_vbus>; mode = "host"; }; usb2-3 { status = "okay"; mode = "host"; }; usb3-0 { status = "okay"; nvidia,lanes = "pcie-6"; nvidia,port = <1>; }; usb3-1 { status = "okay"; nvidia,lanes = "pcie-5"; nvidia,port = <2>; }; }; }; Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +6 −0 Original line number Diff line number Diff line Device tree binding for NVIDIA Tegra XUSB pad controller ======================================================== NOTE: It turns out that this binding isn't an accurate description of the XUSB pad controller. While the description is good enough for the functional subset required for PCIe and SATA, it lacks the flexibility to represent the features needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. The binding described in this file is deprecated and should not be used. The Tegra XUSB pad controller manages a set of lanes, each of which can be assigned to one out of a set of different pads. Some of these pads have an associated PHY that must be powered up before the pad can be used. Loading Documentation/phy.txt +14 −2 Original line number Diff line number Diff line Loading @@ -31,16 +31,28 @@ should provide its own implementation of of_xlate. of_xlate is used only for dt boot case. #define of_phy_provider_register(dev, xlate) \ __of_phy_provider_register((dev), THIS_MODULE, (xlate)) __of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate)) #define devm_of_phy_provider_register(dev, xlate) \ __devm_of_phy_provider_register((dev), THIS_MODULE, (xlate)) __devm_of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate)) of_phy_provider_register and devm_of_phy_provider_register macros can be used to register the phy_provider and it takes device and of_xlate as arguments. For the dt boot case, all PHY providers should use one of the above 2 macros to register the PHY provider. Often the device tree nodes associated with a PHY provider will contain a set of children that each represent a single PHY. Some bindings may nest the child nodes within extra levels for context and extensibility, in which case the low level of_phy_provider_register_full() and devm_of_phy_provider_register_full() macros can be used to override the node containing the children. #define of_phy_provider_register_full(dev, children, xlate) \ __of_phy_provider_register(dev, children, THIS_MODULE, xlate) #define devm_of_phy_provider_register_full(dev, children, xlate) \ __devm_of_phy_provider_register_full(dev, children, THIS_MODULE, xlate) void devm_of_phy_provider_unregister(struct device *dev, struct phy_provider *phy_provider); void of_phy_provider_unregister(struct phy_provider *phy_provider); Loading drivers/clk/tegra/clk-tegra210.c +58 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,19 @@ #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) #define SATA_PLL_CFG0 0x490 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) #define XUSBIO_PLL_CFG0 0x51c #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) #define UTMIPLL_HW_PWRDN_CFG0 0x52c #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) Loading Loading @@ -416,6 +429,51 @@ static const char *mux_pllmcp_clkm[] = { #define PLLU_MISC0_WRITE_MASK 0xbfffffff #define PLLU_MISC1_WRITE_MASK 0x00000007 void tegra210_xusb_pll_hw_control_enable(void) { u32 val; val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); void tegra210_xusb_pll_hw_sequence_start(void) { u32 val; val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); void tegra210_sata_pll_hw_control_enable(void) { u32 val; val = readl_relaxed(clk_base + SATA_PLL_CFG0); val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; writel_relaxed(val, clk_base + SATA_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); void tegra210_sata_pll_hw_sequence_start(void) { u32 val; val = readl_relaxed(clk_base + SATA_PLL_CFG0); val |= SATA_PLL_CFG0_SEQ_ENABLE; writel_relaxed(val, clk_base + SATA_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); static inline void _pll_misc_chk_default(void __iomem *base, struct tegra_clk_pll_params *params, u8 misc_num, u32 default_val, u32 mask) Loading drivers/phy/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -421,4 +421,6 @@ config PHY_CYGNUS_PCIE Enable this to support the Broadcom Cygnus PCIe PHY. If unsure, say N. source "drivers/phy/tegra/Kconfig" endmenu Loading
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt 0 → 100644 +733 −0 Original line number Diff line number Diff line Device tree binding for NVIDIA Tegra XUSB pad controller ======================================================== The Tegra XUSB pad controller manages a set of I/O lanes (with differential signals) which connect directly to pins/pads on the SoC package. Each lane is controlled by a HW block referred to as a "pad" in the Tegra hardware documentation. Each such "pad" may control either one or multiple lanes, and thus contains any logic common to all its lanes. Each lane can be separately configured and powered up. Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or super-speed USB. Other lanes are for various types of low-speed, full-speed or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller contains a software-configurable mux that sits between the I/O controller ports (e.g. PCIe) and the lanes. In addition to per-lane configuration, USB 3.0 ports may require additional settings on a per-board basis. Pads will be represented as children of the top-level XUSB pad controller device tree node. Each lane exposed by the pad will be represented by its own subnode and can be referenced by users of the lane using the standard PHY bindings, as described by the phy-bindings.txt file in this directory. The Tegra hardware documentation refers to the connection between the XUSB pad controller and the XUSB controller as "ports". This is confusing since "port" is typically used to denote the physical USB receptacle. The device tree binding in this document uses the term "port" to refer to the logical abstraction of the signals that are routed to a USB receptacle (i.e. a PHY for the USB signal, the VBUS power supply, the USB 2.0 companion port for USB 3.0 receptacles, ...). Required properties: -------------------- - compatible: Must be: - Tegra124: "nvidia,tegra124-xusb-padctl" - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl" - Tegra210: "nvidia,tegra210-xusb-padctl" - reg: Physical base address and length of the controller's registers. - resets: Must contain an entry for each entry in reset-names. - reset-names: Must include the following entries: - "padctl" Pad nodes: ========== A required child node named "pads" contains a list of subnodes, one for each of the pads exposed by the XUSB pad controller. Each pad may need additional resources that can be referenced in its pad node. The "status" property is used to enable or disable the use of a pad. If set to "disabled", the pad will not be used on the given board. In order to use the pad and any of its lanes, this property must be set to "okay". For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie and sata. No extra resources are required for operation of these pads. For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is a description of the properties of each pad. UTMI pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "trk": phandle and specifier referring to the USB2 tracking clock HSIC pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "trk": phandle and specifier referring to the HSIC tracking clock PCIe pad: --------- Required properties: - clocks: Must contain an entry for each entry in clock-names. - clock-names: Must contain the following entries: - "pll": phandle and specifier referring to the PLLE - resets: Must contain an entry for each entry in reset-names. - reset-names: Must contain the following entries: - "phy": reset for the PCIe UPHY block SATA pad: --------- Required properties: - resets: Must contain an entry for each entry in reset-names. - reset-names: Must contain the following entries: - "phy": reset for the SATA UPHY block PHY nodes: ========== Each pad node has a child named "lanes" that contains one or more children of its own, each representing one of the lanes controlled by the pad. Required properties: -------------------- - status: Defines the operation status of the PHY. Valid values are: - "disabled": the PHY is disabled - "okay": the PHY is enabled - #phy-cells: Should be 0. Since each lane represents a single PHY, there is no need for an additional specifier. - nvidia,function: The output function of the PHY. See below for a list of valid functions per SoC generation. For Tegra124 and Tegra132, the list of valid PHY nodes is given below: - usb2: usb2-0, usb2-1, usb2-2 - functions: "snps", "xusb", "uart" - ulpi: ulpi-0 - functions: "snps", "xusb" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4 - functions: "pcie", "usb3-ss" - sata: sata-0 - functions: "usb3-ss", "sata" For Tegra210, the list of valid PHY nodes is given below: - utmi: utmi-0, utmi-1, utmi-2, utmi-3 - functions: "snps", "xusb", "uart" - hsic: hsic-0, hsic-1 - functions: "snps", "xusb" - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6 - functions: "pcie-x1", "usb3-ss", "pcie-x4" - sata: sata-0 - functions: "usb3-ss", "sata" Port nodes: =========== A required child node named "ports" contains a list of all the ports exposed by the XUSB pad controller. Per-port configuration is only required for USB. USB2 ports: ----------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - mode: A string that determines the mode in which to run the port. Valid values are: - "host": for USB host mode - "device": for USB device mode - "otg": for USB OTG mode Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. - vbus-supply: phandle to a regulator supplying the VBUS voltage. ULPI ports: ----------- Optional properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. - vbus-supply: phandle to a regulator supplying the VBUS voltage. HSIC ports: ----------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled Optional properties: - vbus-supply: phandle to a regulator supplying the VBUS voltage. Super-speed USB ports: ---------------------- Required properties: - status: Defines the operation status of the port. Valid values are: - "disabled": the port is disabled - "okay": the port is enabled - nvidia,usb2-companion: A single cell that specifies the physical port number to map this super-speed USB port to. The range of valid port numbers varies with the SoC generation: - 0-2: for Tegra124 and Tegra132 - 0-3: for Tegra210 Optional properties: - nvidia,internal: A boolean property whose presence determines that a port is internal. In the absence of this property the port is considered to be external. For Tegra124 and Tegra132, the XUSB pad controller exposes the following ports: - 3x USB2: usb2-0, usb2-1, usb2-2 - 1x ULPI: ulpi-0 - 2x HSIC: hsic-0, hsic-1 - 2x super-speed USB: usb3-0, usb3-1 For Tegra210, the XUSB pad controller exposes the following ports: - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3 - 2x HSIC: hsic-0, hsic-1 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3 Examples: ========= Tegra124 and Tegra132: ---------------------- SoC include: padctl@7009f000 { /* for Tegra124 */ compatible = "nvidia,tegra124-xusb-padctl"; /* for Tegra132 */ compatible = "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; pads { usb2 { status = "disabled"; lanes { usb2-0 { status = "disabled"; #phy-cells = <0>; }; usb2-1 { status = "disabled"; #phy-cells = <0>; }; usb2-2 { status = "disabled"; #phy-cells = <0>; }; }; }; ulpi { status = "disabled"; lanes { ulpi-0 { status = "disabled"; #phy-cells = <0>; }; }; }; hsic { status = "disabled"; lanes { hsic-0 { status = "disabled"; #phy-cells = <0>; }; hsic-1 { status = "disabled"; #phy-cells = <0>; }; }; }; pcie { status = "disabled"; lanes { pcie-0 { status = "disabled"; #phy-cells = <0>; }; pcie-1 { status = "disabled"; #phy-cells = <0>; }; pcie-2 { status = "disabled"; #phy-cells = <0>; }; pcie-3 { status = "disabled"; #phy-cells = <0>; }; pcie-4 { status = "disabled"; #phy-cells = <0>; }; }; }; sata { status = "disabled"; lanes { sata-0 { status = "disabled"; #phy-cells = <0>; }; }; }; }; ports { usb2-0 { status = "disabled"; }; usb2-1 { status = "disabled"; }; usb2-2 { status = "disabled"; }; ulpi-0 { status = "disabled"; }; hsic-0 { status = "disabled"; }; hsic-1 { status = "disabled"; }; usb3-0 { status = "disabled"; }; usb3-1 { status = "disabled"; }; }; }; Board file: padctl@7009f000 { status = "okay"; pads { usb2 { status = "okay"; lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; usb2-1 { nvidia,function = "xusb"; status = "okay"; }; usb2-2 { nvidia,function = "xusb"; status = "okay"; }; }; }; pcie { status = "okay"; lanes { pcie-0 { nvidia,function = "usb3-ss"; status = "okay"; }; pcie-2 { nvidia,function = "pcie"; status = "okay"; }; pcie-4 { nvidia,function = "pcie"; status = "okay"; }; }; }; sata { status = "okay"; lanes { sata-0 { nvidia,function = "sata"; status = "okay"; }; }; }; }; ports { /* Micro A/B */ usb2-0 { status = "okay"; mode = "otg"; }; /* Mini PCIe */ usb2-1 { status = "okay"; mode = "host"; }; /* USB3 */ usb2-2 { status = "okay"; mode = "host"; vbus-supply = <&vdd_usb3_vbus>; }; usb3-0 { nvidia,port = <2>; status = "okay"; }; }; }; Tegra210: --------- SoC include: padctl@7009f000 { compatible = "nvidia,tegra210-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; status = "disabled"; pads { usb2 { clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; clock-names = "trk"; status = "disabled"; lanes { usb2-0 { status = "disabled"; #phy-cells = <0>; }; usb2-1 { status = "disabled"; #phy-cells = <0>; }; usb2-2 { status = "disabled"; #phy-cells = <0>; }; usb2-3 { status = "disabled"; #phy-cells = <0>; }; }; }; hsic { clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; clock-names = "trk"; status = "disabled"; lanes { hsic-0 { status = "disabled"; #phy-cells = <0>; }; hsic-1 { status = "disabled"; #phy-cells = <0>; }; }; }; pcie { clocks = <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "pll"; resets = <&tegra_car 205>; reset-names = "phy"; status = "disabled"; lanes { pcie-0 { status = "disabled"; #phy-cells = <0>; }; pcie-1 { status = "disabled"; #phy-cells = <0>; }; pcie-2 { status = "disabled"; #phy-cells = <0>; }; pcie-3 { status = "disabled"; #phy-cells = <0>; }; pcie-4 { status = "disabled"; #phy-cells = <0>; }; pcie-5 { status = "disabled"; #phy-cells = <0>; }; pcie-6 { status = "disabled"; #phy-cells = <0>; }; }; }; sata { clocks = <&tegra_car TEGRA210_CLK_PLL_E>; clock-names = "pll"; resets = <&tegra_car 204>; reset-names = "phy"; status = "disabled"; lanes { sata-0 { status = "disabled"; #phy-cells = <0>; }; }; }; }; ports { usb2-0 { status = "disabled"; }; usb2-1 { status = "disabled"; }; usb2-2 { status = "disabled"; }; usb2-3 { status = "disabled"; }; hsic-0 { status = "disabled"; }; hsic-1 { status = "disabled"; }; usb3-0 { status = "disabled"; }; usb3-1 { status = "disabled"; }; usb3-2 { status = "disabled"; }; usb3-3 { status = "disabled"; }; }; }; Board file: padctl@7009f000 { status = "okay"; pads { usb2 { status = "okay"; lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; usb2-1 { nvidia,function = "xusb"; status = "okay"; }; usb2-2 { nvidia,function = "xusb"; status = "okay"; }; usb2-3 { nvidia,function = "xusb"; status = "okay"; }; }; }; pcie { status = "okay"; lanes { pcie-0 { nvidia,function = "pcie-x1"; status = "okay"; }; pcie-1 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-2 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-3 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-4 { nvidia,function = "pcie-x4"; status = "okay"; }; pcie-5 { nvidia,function = "usb3-ss"; status = "okay"; }; pcie-6 { nvidia,function = "usb3-ss"; status = "okay"; }; }; }; sata { status = "okay"; lanes { sata-0 { nvidia,function = "sata"; status = "okay"; }; }; }; }; ports { usb2-0 { status = "okay"; mode = "otg"; }; usb2-1 { status = "okay"; vbus-supply = <&vdd_5v0_rtl>; mode = "host"; }; usb2-2 { status = "okay"; vbus-supply = <&vdd_usb_vbus>; mode = "host"; }; usb2-3 { status = "okay"; mode = "host"; }; usb3-0 { status = "okay"; nvidia,lanes = "pcie-6"; nvidia,port = <1>; }; usb3-1 { status = "okay"; nvidia,lanes = "pcie-5"; nvidia,port = <2>; }; }; };
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt +6 −0 Original line number Diff line number Diff line Device tree binding for NVIDIA Tegra XUSB pad controller ======================================================== NOTE: It turns out that this binding isn't an accurate description of the XUSB pad controller. While the description is good enough for the functional subset required for PCIe and SATA, it lacks the flexibility to represent the features needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. The binding described in this file is deprecated and should not be used. The Tegra XUSB pad controller manages a set of lanes, each of which can be assigned to one out of a set of different pads. Some of these pads have an associated PHY that must be powered up before the pad can be used. Loading
Documentation/phy.txt +14 −2 Original line number Diff line number Diff line Loading @@ -31,16 +31,28 @@ should provide its own implementation of of_xlate. of_xlate is used only for dt boot case. #define of_phy_provider_register(dev, xlate) \ __of_phy_provider_register((dev), THIS_MODULE, (xlate)) __of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate)) #define devm_of_phy_provider_register(dev, xlate) \ __devm_of_phy_provider_register((dev), THIS_MODULE, (xlate)) __devm_of_phy_provider_register((dev), NULL, THIS_MODULE, (xlate)) of_phy_provider_register and devm_of_phy_provider_register macros can be used to register the phy_provider and it takes device and of_xlate as arguments. For the dt boot case, all PHY providers should use one of the above 2 macros to register the PHY provider. Often the device tree nodes associated with a PHY provider will contain a set of children that each represent a single PHY. Some bindings may nest the child nodes within extra levels for context and extensibility, in which case the low level of_phy_provider_register_full() and devm_of_phy_provider_register_full() macros can be used to override the node containing the children. #define of_phy_provider_register_full(dev, children, xlate) \ __of_phy_provider_register(dev, children, THIS_MODULE, xlate) #define devm_of_phy_provider_register_full(dev, children, xlate) \ __devm_of_phy_provider_register_full(dev, children, THIS_MODULE, xlate) void devm_of_phy_provider_unregister(struct device *dev, struct phy_provider *phy_provider); void of_phy_provider_unregister(struct phy_provider *phy_provider); Loading
drivers/clk/tegra/clk-tegra210.c +58 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,19 @@ #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14) #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12) #define SATA_PLL_CFG0 0x490 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) #define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) #define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) #define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) #define XUSBIO_PLL_CFG0 0x51c #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) #define XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL BIT(2) #define XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET BIT(6) #define XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) #define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) #define UTMIPLL_HW_PWRDN_CFG0 0x52c #define UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK BIT(31) #define UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE BIT(25) Loading Loading @@ -416,6 +429,51 @@ static const char *mux_pllmcp_clkm[] = { #define PLLU_MISC0_WRITE_MASK 0xbfffffff #define PLLU_MISC1_WRITE_MASK 0x00000007 void tegra210_xusb_pll_hw_control_enable(void) { u32 val; val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL | XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL); val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET | XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_control_enable); void tegra210_xusb_pll_hw_sequence_start(void) { u32 val; val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_xusb_pll_hw_sequence_start); void tegra210_sata_pll_hw_control_enable(void) { u32 val; val = readl_relaxed(clk_base + SATA_PLL_CFG0); val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET | SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; writel_relaxed(val, clk_base + SATA_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_control_enable); void tegra210_sata_pll_hw_sequence_start(void) { u32 val; val = readl_relaxed(clk_base + SATA_PLL_CFG0); val |= SATA_PLL_CFG0_SEQ_ENABLE; writel_relaxed(val, clk_base + SATA_PLL_CFG0); } EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); static inline void _pll_misc_chk_default(void __iomem *base, struct tegra_clk_pll_params *params, u8 misc_num, u32 default_val, u32 mask) Loading
drivers/phy/Kconfig +2 −0 Original line number Diff line number Diff line Loading @@ -421,4 +421,6 @@ config PHY_CYGNUS_PCIE Enable this to support the Broadcom Cygnus PCIe PHY. If unsure, say N. source "drivers/phy/tegra/Kconfig" endmenu
