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Commit 3fadf2ab authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

clk: qcom: msm: update the Display Port clocks for SDM845 



Update the clock names for parents of Display Port clocks for
SDM845. Update the clock frequencies of DP clocks as requested by
the Display Port driver in order of KHz to avoid integer
overflow issues on 32-bit builds. Remove the RCG clock for DP
link interface clock since the default divider value of div-4 is
correct and always constant, hence it doesn't need a set rate
propagation to its parent.

Change-Id: I46be984340902f1facba59ad966e0f2ad1b1b006
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent c6d522c5

drivers/clk/qcom/dispcc-sdm845.c

+36 −60
Original line number Diff line number Diff line
@@ -80,8 +80,8 @@ static const struct parent_map disp_cc_parent_map_1[] = { 


static const char * const disp_cc_parent_names_1[] = {

	"bi_tcxo",

	"dp_phy_pll_link_clk",

	"dp_phy_pll_vco_div_clk",

	"dp_link_clk_divsel_ten",

	"dp_vco_divided_clk_src_mux",

	"core_bi_pll_test_se",

};
@@ -217,12 +217,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 
	},

};



/* Need to get the exact frequencies that are supported */

static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = {

	F( 108000000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 180000000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 360000000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 540000000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 108000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 180000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 360000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	{ }

};
@@ -236,23 +235,22 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
		.name = "disp_cc_mdss_dp_crypto_clk_src",

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.flags = CLK_GET_RATE_NOCACHE,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP5(

			MIN, 12800000,

			LOWER, 108000000,

			LOW, 180000000,

			LOW_L1, 360000000,

			NOMINAL, 540000000),

			MIN, 12800,

			LOWER, 108000,

			LOW, 180000,

			LOW_L1, 360000,

			NOMINAL, 540000),

	},

};



/* Need to get the exact frequencies that are supported */

static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {

	F_SLEW( 162000000, P_DP_PHY_PLL_LINK_CLK,   2,   0,   0,  324000000),

	F_SLEW( 270000000, P_DP_PHY_PLL_LINK_CLK,   2,   0,   0,  540000000),

	F_SLEW( 540000000, P_DP_PHY_PLL_LINK_CLK,   2,   0,   0, 1080000000),

	F_SLEW( 810000000, P_DP_PHY_PLL_LINK_CLK,   2,   0,   0, 1620000000),

	F( 162000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 270000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	{ }

};
@@ -269,11 +267,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.ops = &clk_rcg2_ops,

		VDD_CX_FMAX_MAP5(

			MIN, 19200000,

			LOWER, 162000000,

			LOW, 270000000,

			LOW_L1, 540000000,

			NOMINAL, 810000000),

			MIN, 19200,

			LOWER, 162000,

			LOW, 270000,

			LOW_L1, 540000,

			NOMINAL, 810000),

	},

};
@@ -284,17 +282,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { 
	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_pixel1_clk_src",

		.parent_names = (const char *[]){

			"dp_phy_pll_vco_div_clk",

		},

		.num_parents = 1,

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.ops = &clk_dp_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,

			LOWER, 202500000,

			LOW, 296735905,

			LOW_L1, 675000000),

			MIN, 19200,

			LOWER, 202500,

			LOW, 296735,

			LOW_L1, 675000),

	},

};
@@ -305,17 +301,15 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 
	.parent_map = disp_cc_parent_map_1,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "disp_cc_mdss_dp_pixel_clk_src",

		.parent_names = (const char *[]){

			"dp_phy_pll_vco_div_clk",

		},

		.num_parents = 1,

		.parent_names = disp_cc_parent_names_1,

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

		.ops = &clk_dp_ops,

		VDD_CX_FMAX_MAP4(

			MIN, 19200000,

			LOWER, 202500000,

			LOW, 296735905,

			LOW_L1, 675000000),

			MIN, 19200,

			LOWER, 202500,

			LOW, 296735,

			LOW_L1, 675000),

	},

};
@@ -664,23 +658,7 @@ static struct clk_branch disp_cc_mdss_dp_link_clk = { 
	},

};



static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {

	.reg = 0x2150,

	.shift = 0,

	.width = 2,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_link_div_clk_src",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_link_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.ops = &clk_regmap_div_ops,

		},

	},

};



/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */

static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {

	.halt_reg = 0x2044,

	.halt_check = BRANCH_HALT,
@@ -690,10 +668,10 @@ static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_mdss_dp_link_intf_clk",

			.parent_names = (const char *[]){

				"disp_cc_mdss_dp_link_div_clk_src",

				"disp_cc_mdss_dp_link_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

			.flags = CLK_GET_RATE_NOCACHE,

			.ops = &clk_branch2_ops,

		},

	},
@@ -955,8 +933,6 @@ static struct clk_regmap *disp_cc_sdm845_clocks[] = { 
					&disp_cc_mdss_dp_crypto_clk_src.clkr,

	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,

	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,

	[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] =

					&disp_cc_mdss_dp_link_div_clk_src.clkr,

	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,

	[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,

	[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =

include/dt-bindings/clock/qcom,dispcc-sdm845.h

+0 −1
Original line number Diff line number Diff line
@@ -55,7 +55,6 @@ 
#define DISP_CC_PLL0						38

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				39

#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				40

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			41



#define DISP_CC_MDSS_CORE_BCR					0

#define DISP_CC_MDSS_GCC_CLOCKS_BCR				1