Commit 3f73f94a authored Sep 26, 2018 by Suzuki K Poulose Committed by Greg Kroah-Hartman Nov 25, 2019

kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table



[ Upstream commit d2db7773ba864df6b4e19643dfc54838550d8049 ]

So far we have only supported 3 level page table with fixed IPA of
40bits, where PUD is folded. With 4 level page tables, we need
to check if the PUD entry is valid or not. Fix stage2_flush_memslot()
to do this check, before walking down the table.

Acked-by: Christoffer Dall <cdall@kernel.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 3d827805

arch/arm/kvm/mmu.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -366,6 +366,7 @@ static void stage2_flush_memslot(struct kvm *kvm,
		pgd = kvm->arch.pgd + stage2_pgd_index(addr);
		do {
		next = stage2_pgd_addr_end(addr, end);
		if (!stage2_pgd_none(*pgd))
		stage2_flush_puds(kvm, pgd, addr, next);
		} while (pgd++, addr = next, addr != end);
		}