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Commit 3ea4807d authored by Marcelo Tosatti's avatar Marcelo Tosatti Committed by Paul Mackerras
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[PATCH] powerpc/8xx: last two 8MB D-TLB entries are incorrectly set 



The last two 8MB TLB entries are being incorrectly set by initial_mmu on 8xx.

The first entry is written with the same virtual/physical address, which
renders it invalid:

BDI>rms 792 0x00001e00
BDI>rms 824 1
BDI>rds 824
SPR  824 : 0xc08000c0  -1065353024
BDI>rds 825
SPR  825 : 0xc0800de0  -1065349664
BDI>rds 826
SPR  826 : 0x00000000            0

And the second entry, in addition, does not have its TLB index set
correctly.

Signed-off-by: default avatarMarcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent aee9f265

arch/ppc/kernel/head_8xx.S

+5 −2
Original line number Diff line number Diff line
@@ -810,13 +810,16 @@ initial_mmu: 
	mtspr	SPRN_MD_TWC, r9

	li	r11, MI_BOOTINIT	/* Create RPN for address 0 */

	addis	r11, r11, 0x0080	/* Add 8M */

	mtspr	SPRN_MD_RPN, r8

	mtspr	SPRN_MD_RPN, r11



	addi	r10, r10, 0x0100

	mtspr	SPRN_MD_CTR, r10



	addis	r8, r8, 0x0080		/* Add 8M */

	mtspr	SPRN_MD_EPN, r8

	mtspr	SPRN_MD_TWC, r9

	addis	r11, r11, 0x0080	/* Add 8M */

	mtspr	SPRN_MD_RPN, r8

	mtspr	SPRN_MD_RPN, r11

#endif



	/* Since the cache is enabled according to the information we