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Commit 3e940b6a authored by Ben Dooks's avatar Ben Dooks Committed by Russell King
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[ARM] 4044/1: S3C24XX: fix sparse warnings in arch/arm/mach-s3c2410/s3c2442-clock.c 



Fix sparse errors in arch/arm/mach-s3c2410/s3c2442-clock.c

warning: symbol 'clk_h' shadows an earlier one
warning: symbol 'clk_p' shadows an earlier one
warning: symbol 'clk_upll' shadows an earlier one

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e546e8af

arch/arm/mach-s3c2410/s3c2442-clock.c

+11 −11
Original line number Diff line number Diff line
@@ -117,18 +117,18 @@ static int s3c2442_clk_add(struct sys_device *sysdev) 
{

	unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);

	unsigned long clkdivn;

	struct clk *clk_h;

	struct clk *clk_p;

	struct clk *clk_upll;

	struct clk *clock_h;

	struct clk *clock_p;

	struct clk *clock_upll;



	printk("S3C2442: Clock Support, DVS %s\n",

	       (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");



	clk_p = clk_get(NULL, "pclk");

	clk_h = clk_get(NULL, "hclk");

	clk_upll = clk_get(NULL, "upll");

	clock_p = clk_get(NULL, "pclk");

	clock_h = clk_get(NULL, "hclk");

	clock_upll = clk_get(NULL, "upll");



	if (IS_ERR(clk_p) || IS_ERR(clk_h) || IS_ERR(clk_upll)) {

	if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {

		printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");

		return -EINVAL;

	}
@@ -136,8 +136,8 @@ static int s3c2442_clk_add(struct sys_device *sysdev) 
	/* check rate of UPLL, and if it is near 96MHz, then change

	 * to using half the UPLL rate for the system */



	if (clk_get_rate(clk_upll) > (94 * MHZ)) {

		clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;

	if (clk_get_rate(clock_upll) > (94 * MHZ)) {

		clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;



		mutex_lock(&clocks_mutex);
@@ -148,8 +148,8 @@ static int s3c2442_clk_add(struct sys_device *sysdev) 
		mutex_unlock(&clocks_mutex);

	}



	s3c2442_clk_cam.parent = clk_h;

	s3c2442_clk_cam_upll.parent = clk_upll;

	s3c2442_clk_cam.parent = clock_h;

	s3c2442_clk_cam_upll.parent = clock_upll;



	s3c24xx_register_clock(&s3c2442_clk_cam);

	s3c24xx_register_clock(&s3c2442_clk_cam_upll);