Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3e6c4538 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
Browse files

sfc: Update hardware definitions for Siena 



Siena is still based on the Falcon hardware architecture and will
share many of these definitions, so replace falcon_hwdefs.h with
regs.h.

The new definitions have been generated according to a naming
convention which incorporates the type and revision information.
Update the code accordingly.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 625b4514

drivers/net/sfc/falcon.c

+437 −411

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/sfc/falcon_boards.c

+7 −7
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
#include "phy.h"

#include "efx.h"

#include "falcon.h"

#include "falcon_hwdefs.h"

#include "regs.h"

#include "falcon_io.h"

#include "workarounds.h"
@@ -332,14 +332,14 @@ static int sfn4111t_reset(struct efx_nic *efx) 
	 * FLASH_CFG_1 strap (GPIO 3) appropriately.  Only change the

	 * output enables; the output levels should always be 0 (low)

	 * and we rely on external pull-ups. */

	falcon_read(efx, &reg, GPIO_CTL_REG_KER);

	EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, true);

	falcon_write(efx, &reg, GPIO_CTL_REG_KER);

	falcon_read(efx, &reg, FR_AB_GPIO_CTL);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);

	falcon_write(efx, &reg, FR_AB_GPIO_CTL);

	msleep(1000);

	EFX_SET_OWORD_FIELD(reg, GPIO2_OEN, false);

	EFX_SET_OWORD_FIELD(reg, GPIO3_OEN,

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,

			    !!(efx->phy_mode & PHY_MODE_SPECIAL));

	falcon_write(efx, &reg, GPIO_CTL_REG_KER);

	falcon_write(efx, &reg, FR_AB_GPIO_CTL);

	msleep(1);



	mutex_unlock(&efx->i2c_adap.bus_lock);

drivers/net/sfc/falcon_gmac.c

+46 −46
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
#include "efx.h"

#include "falcon.h"

#include "mac.h"

#include "falcon_hwdefs.h"

#include "regs.h"

#include "falcon_io.h"



/**************************************************************************
@@ -36,89 +36,89 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx) 
	bytemode = (efx->link_speed == 1000);



	EFX_POPULATE_OWORD_5(reg,

			     GM_LOOP, loopback,

			     GM_TX_EN, 1,

			     GM_TX_FC_EN, tx_fc,

			     GM_RX_EN, 1,

			     GM_RX_FC_EN, rx_fc);

	falcon_write(efx, &reg, GM_CFG1_REG);

			     FRF_AB_GM_LOOP, loopback,

			     FRF_AB_GM_TX_EN, 1,

			     FRF_AB_GM_TX_FC_EN, tx_fc,

			     FRF_AB_GM_RX_EN, 1,

			     FRF_AB_GM_RX_FC_EN, rx_fc);

	falcon_write(efx, &reg, FR_AB_GM_CFG1);

	udelay(10);



	/* Configuration register 2 */

	if_mode = (bytemode) ? 2 : 1;

	EFX_POPULATE_OWORD_5(reg,

			     GM_IF_MODE, if_mode,

			     GM_PAD_CRC_EN, 1,

			     GM_LEN_CHK, 1,

			     GM_FD, efx->link_fd,

			     GM_PAMBL_LEN, 0x7/*datasheet recommended */);

			     FRF_AB_GM_IF_MODE, if_mode,

			     FRF_AB_GM_PAD_CRC_EN, 1,

			     FRF_AB_GM_LEN_CHK, 1,

			     FRF_AB_GM_FD, efx->link_fd,

			     FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */);



	falcon_write(efx, &reg, GM_CFG2_REG);

	falcon_write(efx, &reg, FR_AB_GM_CFG2);

	udelay(10);



	/* Max frame len register */

	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);

	EFX_POPULATE_OWORD_1(reg, GM_MAX_FLEN, max_frame_len);

	falcon_write(efx, &reg, GM_MAX_FLEN_REG);

	EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len);

	falcon_write(efx, &reg, FR_AB_GM_MAX_FLEN);

	udelay(10);



	/* FIFO configuration register 0 */

	EFX_POPULATE_OWORD_5(reg,

			     GMF_FTFENREQ, 1,

			     GMF_STFENREQ, 1,

			     GMF_FRFENREQ, 1,

			     GMF_SRFENREQ, 1,

			     GMF_WTMENREQ, 1);

	falcon_write(efx, &reg, GMF_CFG0_REG);

			     FRF_AB_GMF_FTFENREQ, 1,

			     FRF_AB_GMF_STFENREQ, 1,

			     FRF_AB_GMF_FRFENREQ, 1,

			     FRF_AB_GMF_SRFENREQ, 1,

			     FRF_AB_GMF_WTMENREQ, 1);

	falcon_write(efx, &reg, FR_AB_GMF_CFG0);

	udelay(10);



	/* FIFO configuration register 1 */

	EFX_POPULATE_OWORD_2(reg,

			     GMF_CFGFRTH, 0x12,

			     GMF_CFGXOFFRTX, 0xffff);

	falcon_write(efx, &reg, GMF_CFG1_REG);

			     FRF_AB_GMF_CFGFRTH, 0x12,

			     FRF_AB_GMF_CFGXOFFRTX, 0xffff);

	falcon_write(efx, &reg, FR_AB_GMF_CFG1);

	udelay(10);



	/* FIFO configuration register 2 */

	EFX_POPULATE_OWORD_2(reg,

			     GMF_CFGHWM, 0x3f,

			     GMF_CFGLWM, 0xa);

	falcon_write(efx, &reg, GMF_CFG2_REG);

			     FRF_AB_GMF_CFGHWM, 0x3f,

			     FRF_AB_GMF_CFGLWM, 0xa);

	falcon_write(efx, &reg, FR_AB_GMF_CFG2);

	udelay(10);



	/* FIFO configuration register 3 */

	EFX_POPULATE_OWORD_2(reg,

			     GMF_CFGHWMFT, 0x1c,

			     GMF_CFGFTTH, 0x08);

	falcon_write(efx, &reg, GMF_CFG3_REG);

			     FRF_AB_GMF_CFGHWMFT, 0x1c,

			     FRF_AB_GMF_CFGFTTH, 0x08);

	falcon_write(efx, &reg, FR_AB_GMF_CFG3);

	udelay(10);



	/* FIFO configuration register 4 */

	EFX_POPULATE_OWORD_1(reg, GMF_HSTFLTRFRM_PAUSE, 1);

	falcon_write(efx, &reg, GMF_CFG4_REG);

	EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1);

	falcon_write(efx, &reg, FR_AB_GMF_CFG4);

	udelay(10);



	/* FIFO configuration register 5 */

	falcon_read(efx, &reg, GMF_CFG5_REG);

	EFX_SET_OWORD_FIELD(reg, GMF_CFGBYTMODE, bytemode);

	EFX_SET_OWORD_FIELD(reg, GMF_CFGHDPLX, !efx->link_fd);

	EFX_SET_OWORD_FIELD(reg, GMF_HSTDRPLT64, !efx->link_fd);

	EFX_SET_OWORD_FIELD(reg, GMF_HSTFLTRFRMDC_PAUSE, 0);

	falcon_write(efx, &reg, GMF_CFG5_REG);

	falcon_read(efx, &reg, FR_AB_GMF_CFG5);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !efx->link_fd);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !efx->link_fd);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0);

	falcon_write(efx, &reg, FR_AB_GMF_CFG5);

	udelay(10);



	/* MAC address */

	EFX_POPULATE_OWORD_4(reg,

			     GM_HWADDR_5, efx->net_dev->dev_addr[5],

			     GM_HWADDR_4, efx->net_dev->dev_addr[4],

			     GM_HWADDR_3, efx->net_dev->dev_addr[3],

			     GM_HWADDR_2, efx->net_dev->dev_addr[2]);

	falcon_write(efx, &reg, GM_ADR1_REG);

			     FRF_AB_GM_ADR_B0, efx->net_dev->dev_addr[5],

			     FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4],

			     FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3],

			     FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]);

	falcon_write(efx, &reg, FR_AB_GM_ADR1);

	udelay(10);

	EFX_POPULATE_OWORD_2(reg,

			     GM_HWADDR_1, efx->net_dev->dev_addr[1],

			     GM_HWADDR_0, efx->net_dev->dev_addr[0]);

	falcon_write(efx, &reg, GM_ADR2_REG);

			     FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1],

			     FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]);

	falcon_write(efx, &reg, FR_AB_GM_ADR2);

	udelay(10);



	falcon_reconfigure_mac_wrapper(efx);

drivers/net/sfc/falcon_hwdefs.h

deleted100644 → 0
+0 −1332

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/net/sfc/falcon_xmac.c

+85 −90
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include "net_driver.h"

#include "efx.h"

#include "falcon.h"

#include "falcon_hwdefs.h"

#include "regs.h"

#include "falcon_io.h"

#include "mac.h"

#include "mdio_10g.h"
@@ -35,27 +35,27 @@ static void falcon_setup_xaui(struct efx_nic *efx) 
	if (efx->phy_type == PHY_TYPE_NONE)

		return;



	falcon_read(efx, &sdctl, XX_SD_CTL_REG);

	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);

	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);

	falcon_write(efx, &sdctl, XX_SD_CTL_REG);

	falcon_read(efx, &sdctl, FR_AB_XX_SD_CTL);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);

	EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);

	falcon_write(efx, &sdctl, FR_AB_XX_SD_CTL);



	EFX_POPULATE_OWORD_8(txdrv,

			     XX_DEQD, XX_TXDRV_DEQ_DEFAULT,

			     XX_DEQC, XX_TXDRV_DEQ_DEFAULT,

			     XX_DEQB, XX_TXDRV_DEQ_DEFAULT,

			     XX_DEQA, XX_TXDRV_DEQ_DEFAULT,

			     XX_DTXD, XX_TXDRV_DTX_DEFAULT,

			     XX_DTXC, XX_TXDRV_DTX_DEFAULT,

			     XX_DTXB, XX_TXDRV_DTX_DEFAULT,

			     XX_DTXA, XX_TXDRV_DTX_DEFAULT);

	falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);

			     FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,

			     FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,

			     FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,

			     FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,

			     FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,

			     FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,

			     FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,

			     FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);

	falcon_write(efx, &txdrv, FR_AB_XX_TXDRV_CTL);

}



int falcon_reset_xaui(struct efx_nic *efx)
@@ -64,14 +64,14 @@ int falcon_reset_xaui(struct efx_nic *efx) 
	int count;



	/* Start reset sequence */

	EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);

	falcon_write(efx, &reg, XX_PWR_RST_REG);

	EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);

	falcon_write(efx, &reg, FR_AB_XX_PWR_RST);



	/* Wait up to 10 ms for completion, then reinitialise */

	for (count = 0; count < 1000; count++) {

		falcon_read(efx, &reg, XX_PWR_RST_REG);

		if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0 &&

		    EFX_OWORD_FIELD(reg, XX_SD_RST_ACT) == 0) {

		falcon_read(efx, &reg, FR_AB_XX_PWR_RST);

		if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&

		    EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {

			falcon_setup_xaui(efx);

			return 0;

		}
@@ -99,12 +99,12 @@ static void falcon_mask_status_intr(struct efx_nic *efx, bool enable) 


	/* Flush the ISR */

	if (enable)

		falcon_read(efx, &reg, XM_MGT_INT_REG_B0);

		falcon_read(efx, &reg, FR_AB_XM_MGT_INT_MSK);



	EFX_POPULATE_OWORD_2(reg,

			     XM_MSK_RMTFLT, !enable,

			     XM_MSK_LCLFLT, !enable);

	falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);

			     FRF_AB_XM_MSK_RMTFLT, !enable,

			     FRF_AB_XM_MSK_LCLFLT, !enable);

	falcon_write(efx, &reg, FR_AB_XM_MGT_INT_MASK);

}



/* Get status of XAUI link */
@@ -118,18 +118,18 @@ bool falcon_xaui_link_ok(struct efx_nic *efx) 
		return true;



	/* Read link status */

	falcon_read(efx, &reg, XX_CORE_STAT_REG);

	falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);



	align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);

	sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);

	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))

	align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);

	sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);

	if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))

		link_ok = true;



	/* Clear link status ready for next read */

	EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);

	EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);

	EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);

	falcon_write(efx, &reg, XX_CORE_STAT_REG);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);

	falcon_write(efx, &reg, FR_AB_XX_CORE_STAT);



	/* If the link is up, then check the phy side of the xaui link */

	if (efx->link_up && link_ok)
@@ -147,55 +147,49 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 


	/* Configure MAC  - cut-thru mode is hard wired on */

	EFX_POPULATE_DWORD_3(reg,

			     XM_RX_JUMBO_MODE, 1,

			     XM_TX_STAT_EN, 1,

			     XM_RX_STAT_EN, 1);

	falcon_write(efx, &reg, XM_GLB_CFG_REG);

			     FRF_AB_XM_RX_JUMBO_MODE, 1,

			     FRF_AB_XM_TX_STAT_EN, 1,

			     FRF_AB_XM_RX_STAT_EN, 1);

	falcon_write(efx, &reg, FR_AB_XM_GLB_CFG);



	/* Configure TX */

	EFX_POPULATE_DWORD_6(reg,

			     XM_TXEN, 1,

			     XM_TX_PRMBL, 1,

			     XM_AUTO_PAD, 1,

			     XM_TXCRC, 1,

			     XM_FCNTL, 1,

			     XM_IPG, 0x3);

	falcon_write(efx, &reg, XM_TX_CFG_REG);

			     FRF_AB_XM_TXEN, 1,

			     FRF_AB_XM_TX_PRMBL, 1,

			     FRF_AB_XM_AUTO_PAD, 1,

			     FRF_AB_XM_TXCRC, 1,

			     FRF_AB_XM_FCNTL, 1,

			     FRF_AB_XM_IPG, 0x3);

	falcon_write(efx, &reg, FR_AB_XM_TX_CFG);



	/* Configure RX */

	EFX_POPULATE_DWORD_5(reg,

			     XM_RXEN, 1,

			     XM_AUTO_DEPAD, 0,

			     XM_ACPT_ALL_MCAST, 1,

			     XM_ACPT_ALL_UCAST, efx->promiscuous,

			     XM_PASS_CRC_ERR, 1);

	falcon_write(efx, &reg, XM_RX_CFG_REG);

			     FRF_AB_XM_RXEN, 1,

			     FRF_AB_XM_AUTO_DEPAD, 0,

			     FRF_AB_XM_ACPT_ALL_MCAST, 1,

			     FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,

			     FRF_AB_XM_PASS_CRC_ERR, 1);

	falcon_write(efx, &reg, FR_AB_XM_RX_CFG);



	/* Set frame length */

	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);

	EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);

	falcon_write(efx, &reg, XM_RX_PARAM_REG);

	EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);

	falcon_write(efx, &reg, FR_AB_XM_RX_PARAM);

	EFX_POPULATE_DWORD_2(reg,

			     XM_MAX_TX_FRM_SIZE, max_frame_len,

			     XM_TX_JUMBO_MODE, 1);

	falcon_write(efx, &reg, XM_TX_PARAM_REG);

			     FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,

			     FRF_AB_XM_TX_JUMBO_MODE, 1);

	falcon_write(efx, &reg, FR_AB_XM_TX_PARAM);



	EFX_POPULATE_DWORD_2(reg,

			     XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */

			     XM_DIS_FCNTL, !rx_fc);

	falcon_write(efx, &reg, XM_FC_REG);

			     FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */

			     FRF_AB_XM_DIS_FCNTL, !rx_fc);

	falcon_write(efx, &reg, FR_AB_XM_FC);



	/* Set MAC address */

	EFX_POPULATE_DWORD_4(reg,

			     XM_ADR_0, efx->net_dev->dev_addr[0],

			     XM_ADR_1, efx->net_dev->dev_addr[1],

			     XM_ADR_2, efx->net_dev->dev_addr[2],

			     XM_ADR_3, efx->net_dev->dev_addr[3]);

	falcon_write(efx, &reg, XM_ADR_LO_REG);

	EFX_POPULATE_DWORD_2(reg,

			     XM_ADR_4, efx->net_dev->dev_addr[4],

			     XM_ADR_5, efx->net_dev->dev_addr[5]);

	falcon_write(efx, &reg, XM_ADR_HI_REG);

	memcpy(&reg, &efx->net_dev->dev_addr[0], 4);

	falcon_write(efx, &reg, FR_AB_XM_ADR_LO);

	memcpy(&reg, &efx->net_dev->dev_addr[4], 2);

	falcon_write(efx, &reg, FR_AB_XM_ADR_HI);

}



static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
@@ -211,12 +205,13 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 
		bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;

		bool reset_xgxs;



		falcon_read(efx, &reg, XX_CORE_STAT_REG);

		old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);

		old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);

		falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);

		old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);

		old_xgmii_loopback =

			EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);



		falcon_read(efx, &reg, XX_SD_CTL_REG);

		old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);

		falcon_read(efx, &reg, FR_AB_XX_SD_CTL);

		old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);



		/* The PHY driver may have turned XAUI off */

		reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
@@ -227,20 +222,20 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 
			falcon_reset_xaui(efx);

	}



	falcon_read(efx, &reg, XX_CORE_STAT_REG);

	EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,

	falcon_read(efx, &reg, FR_AB_XX_CORE_STAT);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,

			    (xgxs_loopback || xaui_loopback) ?

			    XX_FORCE_SIG_DECODE_FORCED : 0);

	EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);

	EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);

	falcon_write(efx, &reg, XX_CORE_STAT_REG);



	falcon_read(efx, &reg, XX_SD_CTL_REG);

	EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);

	falcon_write(efx, &reg, XX_SD_CTL_REG);

			    FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);

	falcon_write(efx, &reg, FR_AB_XX_CORE_STAT);



	falcon_read(efx, &reg, FR_AB_XX_SD_CTL);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);

	EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);

	falcon_write(efx, &reg, FR_AB_XX_SD_CTL);

}