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Commit 3e668f34 authored by Vijayavardhan Vennapusa's avatar Vijayavardhan Vennapusa Committed by Mayank Rana
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USB: dwc3-msm: Add support for setting specific frequency for core clock



Add support for setting USB core clock to particular frequency so that
core clock frequency can be passed through dts property.

Change-Id: If9ff41037d22d7be7f09c9468e8d4cc92280a28e
Signed-off-by: default avatarVijayavardhan Vennapusa <vvreddy@codeaurora.org>
Signed-off-by: default avatarMayank Rana <mrana@codeaurora.org>
parent 52b53aca
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+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ Optional properties :
- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode.
- qcom,disable-host-mode-pm: If present, it disables XHCI PM runtime functionality when USB
  host mode is used.
- qcom,core-clk-rate: If present, indicates clock frequency to be set for USB master clock.
- extcon: phandles to external connector devices. First phandle should point to
	  external connector, which provide "USB" cable events, the second
	  should point to external connector device, which provide "USB-HOST"
+14 −5
Original line number Diff line number Diff line
@@ -2322,14 +2322,23 @@ static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc)
		return PTR_ERR(mdwc->core_reset);
	}

	if (!of_property_read_u32(mdwc->dev->of_node, "qcom,core-clk-rate",
				(u32 *)&mdwc->core_clk_rate)) {
		mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk,
							mdwc->core_clk_rate);
	} else {
		/*
		 * Get Max supported clk frequency for USB Core CLK and request
		 * to set the same.
		 */
		mdwc->core_clk_rate = clk_round_rate(mdwc->core_clk, LONG_MAX);
	}

	if (IS_ERR_VALUE(mdwc->core_clk_rate)) {
		dev_err(mdwc->dev, "fail to get core clk max freq.\n");
	} else {
		dev_dbg(mdwc->dev, "USB core frequency = %ld\n",
							mdwc->core_clk_rate);
		ret = clk_set_rate(mdwc->core_clk, mdwc->core_clk_rate);
		if (ret)
			dev_err(mdwc->dev, "fail to set core_clk freq:%d\n",