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Commit 3db5ca27 authored by Tero Kristo's avatar Tero Kristo Committed by Stephen Boyd
Browse files

clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec 



AM33xx/AM43xx devices use the same DPLL IP blocks, which only support
maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type
DPLLs [2]. Reflect this limitation in the DPLL init code by adding the
max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent c5cc2a0b

drivers/clk/ti/dpll.c

+5 −0
Original line number Diff line number Diff line
@@ -655,6 +655,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) 
		.max_multiplier = 2047,

		.max_divider = 128,

		.min_divider = 1,

		.max_rate = 1000000000,

		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	};
@@ -674,6 +675,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) 
		.max_divider = 256,

		.min_divider = 2,

		.flags = DPLL_J_TYPE,

		.max_rate = 2000000000,

		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	};
@@ -692,6 +694,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) 
		.max_multiplier = 2047,

		.max_divider = 128,

		.min_divider = 1,

		.max_rate = 2000000000,

		.flags = DPLL_J_TYPE,

		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	};
@@ -712,6 +715,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) 
		.max_multiplier = 2047,

		.max_divider = 128,

		.min_divider = 1,

		.max_rate = 1000000000,

		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	};
@@ -729,6 +733,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node) 
		.max_multiplier = 2047,

		.max_divider = 128,

		.min_divider = 1,

		.max_rate = 1000000000,

		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),

	};