Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3d854120 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Michael Turquette:
 "The first set of clk fixes for 4.1 are all driver bugs, with the
  exception of a single locking fix in the core code.

  All driver fixes are for code that was merged recently.  The Samsung
  stuff is mostly fixes around suspend/resume, the Qualcomm fixes are
  for invalid hardware configuration data and the Silicon Labs patches
  are fixes following their move away from platform_data to Device Tree"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: si5351: Do not pass struct clk in platform_data
  clk: si5351: Mention clock-names in the binding documentation
  clk: add missing lock when call clk_core_enable in clk_set_parent
  clk: exynos5420: Restore GATE_BUS_TOP on suspend
  clk: qcom: Fix MSM8916 gfx3d_clk_src configuration
  clk: qcom: Fix MSM8916 venus divider value
  clk: exynos5433: Fix wrong PMS value of exynos5433_pll_rates
  clk: exynos5433: Fix wrong parent clock of sclk_apollo clock
  clk: exynos5433: Fix CLK_PCLK_MONOTONIC_CNT clk register assignment
  clk: exynos5433: Fix wrong offset of PCLK_MSCL_SECURE_SMMU_JPEG
  clk: Use CONFIG_ARCH_EXYNOS instead of CONFIG_ARCH_EXYNOS5433
parents 4cce593f 0cd3be6e

Documentation/devicetree/bindings/clock/silabs,si5351.txt

+3 −1
Original line number Diff line number Diff line
@@ -17,7 +17,8 @@ Required properties: 
- #clock-cells: from common clock binding; shall be set to 1.

- clocks: from common clock binding; list of parent clock

  handles, shall be xtal reference clock or xtal and clkin for

  si5351c only.

  si5351c only. Corresponding clock input names are "xtal" and

  "clkin" respectively.

- #address-cells: shall be set to 1.

- #size-cells: shall be set to 0.
@@ -71,6 +72,7 @@ i2c-master-node { 


		/* connect xtal input to 25MHz reference */

		clocks = <&ref25>;

		clock-names = "xtal";



		/* connect xtal input as source of pll0 and pll1 */

		silabs,pll-source = <0 0>, <1 0>;

drivers/clk/clk-si5351.c

+45 −18
Original line number Diff line number Diff line
@@ -1128,13 +1128,6 @@ static int si5351_dt_parse(struct i2c_client *client, 
	if (!pdata)

		return -ENOMEM;



	pdata->clk_xtal = of_clk_get(np, 0);

	if (!IS_ERR(pdata->clk_xtal))

		clk_put(pdata->clk_xtal);

	pdata->clk_clkin = of_clk_get(np, 1);

	if (!IS_ERR(pdata->clk_clkin))

		clk_put(pdata->clk_clkin);



	/*

	 * property silabs,pll-source : <num src>, [<..>]

	 * allow to selectively set pll source
@@ -1328,8 +1321,22 @@ static int si5351_i2c_probe(struct i2c_client *client, 
	i2c_set_clientdata(client, drvdata);

	drvdata->client = client;

	drvdata->variant = variant;

	drvdata->pxtal = pdata->clk_xtal;

	drvdata->pclkin = pdata->clk_clkin;

	drvdata->pxtal = devm_clk_get(&client->dev, "xtal");

	drvdata->pclkin = devm_clk_get(&client->dev, "clkin");



	if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||

	    PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)

		return -EPROBE_DEFER;



	/*

	 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,

	 *   VARIANT_C can have CLKIN instead.

	 */

	if (IS_ERR(drvdata->pxtal) &&

	    (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {

		dev_err(&client->dev, "missing parent clock\n");

		return -EINVAL;

	}



	drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);

	if (IS_ERR(drvdata->regmap)) {
@@ -1393,6 +1400,11 @@ static int si5351_i2c_probe(struct i2c_client *client, 
		}

	}



	if (!IS_ERR(drvdata->pxtal))

		clk_prepare_enable(drvdata->pxtal);

	if (!IS_ERR(drvdata->pclkin))

		clk_prepare_enable(drvdata->pclkin);



	/* register xtal input clock gate */

	memset(&init, 0, sizeof(init));

	init.name = si5351_input_names[0];
@@ -1407,7 +1419,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
	clk = devm_clk_register(&client->dev, &drvdata->xtal);

	if (IS_ERR(clk)) {

		dev_err(&client->dev, "unable to register %s\n", init.name);

		return PTR_ERR(clk);

		ret = PTR_ERR(clk);

		goto err_clk;

	}



	/* register clkin input clock gate */
@@ -1425,7 +1438,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
		if (IS_ERR(clk)) {

			dev_err(&client->dev, "unable to register %s\n",

				init.name);

			return PTR_ERR(clk);

			ret = PTR_ERR(clk);

			goto err_clk;

		}

	}
@@ -1447,7 +1461,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
	clk = devm_clk_register(&client->dev, &drvdata->pll[0].hw);

	if (IS_ERR(clk)) {

		dev_err(&client->dev, "unable to register %s\n", init.name);

		return -EINVAL;

		ret = PTR_ERR(clk);

		goto err_clk;

	}



	/* register PLLB or VXCO (Si5351B) */
@@ -1471,7 +1486,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
	clk = devm_clk_register(&client->dev, &drvdata->pll[1].hw);

	if (IS_ERR(clk)) {

		dev_err(&client->dev, "unable to register %s\n", init.name);

		return -EINVAL;

		ret = PTR_ERR(clk);

		goto err_clk;

	}



	/* register clk multisync and clk out divider */
@@ -1492,8 +1508,10 @@ static int si5351_i2c_probe(struct i2c_client *client, 
		num_clocks * sizeof(*drvdata->onecell.clks), GFP_KERNEL);



	if (WARN_ON(!drvdata->msynth || !drvdata->clkout ||

		    !drvdata->onecell.clks))

		return -ENOMEM;

		    !drvdata->onecell.clks)) {

		ret = -ENOMEM;

		goto err_clk;

	}



	for (n = 0; n < num_clocks; n++) {

		drvdata->msynth[n].num = n;
@@ -1511,7 +1529,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
		if (IS_ERR(clk)) {

			dev_err(&client->dev, "unable to register %s\n",

				init.name);

			return -EINVAL;

			ret = PTR_ERR(clk);

			goto err_clk;

		}

	}
@@ -1538,7 +1557,8 @@ static int si5351_i2c_probe(struct i2c_client *client, 
		if (IS_ERR(clk)) {

			dev_err(&client->dev, "unable to register %s\n",

				init.name);

			return -EINVAL;

			ret = PTR_ERR(clk);

			goto err_clk;

		}

		drvdata->onecell.clks[n] = clk;
@@ -1557,10 +1577,17 @@ static int si5351_i2c_probe(struct i2c_client *client, 
				  &drvdata->onecell);

	if (ret) {

		dev_err(&client->dev, "unable to add clk provider\n");

		return ret;

		goto err_clk;

	}



	return 0;



err_clk:

	if (!IS_ERR(drvdata->pxtal))

		clk_disable_unprepare(drvdata->pxtal);

	if (!IS_ERR(drvdata->pclkin))

		clk_disable_unprepare(drvdata->pclkin);

	return ret;

}



static const struct i2c_device_id si5351_i2c_ids[] = {

drivers/clk/clk.c

+8 −0
Original line number Diff line number Diff line
@@ -1475,8 +1475,10 @@ static struct clk_core *__clk_set_parent_before(struct clk_core *clk, 
	 */

	if (clk->prepare_count) {

		clk_core_prepare(parent);

		flags = clk_enable_lock();

		clk_core_enable(parent);

		clk_core_enable(clk);

		clk_enable_unlock(flags);

	}



	/* update the clk tree topology */
@@ -1491,13 +1493,17 @@ static void __clk_set_parent_after(struct clk_core *core, 
				   struct clk_core *parent,

				   struct clk_core *old_parent)

{

	unsigned long flags;



	/*

	 * Finish the migration of prepare state and undo the changes done

	 * for preventing a race with clk_enable().

	 */

	if (core->prepare_count) {

		flags = clk_enable_lock();

		clk_core_disable(core);

		clk_core_disable(old_parent);

		clk_enable_unlock(flags);

		clk_core_unprepare(old_parent);

	}

}
@@ -1525,8 +1531,10 @@ static int __clk_set_parent(struct clk_core *clk, struct clk_core *parent, 
		clk_enable_unlock(flags);



		if (clk->prepare_count) {

			flags = clk_enable_lock();

			clk_core_disable(clk);

			clk_core_disable(parent);

			clk_enable_unlock(flags);

			clk_core_unprepare(parent);

		}

		return ret;

drivers/clk/qcom/gcc-msm8916.c

+2 −2
Original line number Diff line number Diff line
@@ -71,8 +71,8 @@ static const char *gcc_xo_gpll0_bimc[] = { 
static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map[] = {

	{ P_XO, 0 },

	{ P_GPLL0_AUX, 3 },

	{ P_GPLL2_AUX, 2 },

	{ P_GPLL1, 1 },

	{ P_GPLL2_AUX, 2 },

};



static const char *gcc_xo_gpll0a_gpll1_gpll2a[] = {
@@ -1115,7 +1115,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { 
static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {

	F(100000000, P_GPLL0, 8, 0, 0),

	F(160000000, P_GPLL0, 5, 0, 0),

	F(228570000, P_GPLL0, 5, 0, 0),

	F(228570000, P_GPLL0, 3.5, 0, 0),

	{ }

};

drivers/clk/samsung/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 
obj-$(CONFIG_SOC_EXYNOS5260)	+= clk-exynos5260.o

obj-$(CONFIG_SOC_EXYNOS5410)	+= clk-exynos5410.o

obj-$(CONFIG_SOC_EXYNOS5420)	+= clk-exynos5420.o

obj-$(CONFIG_ARCH_EXYNOS5433)	+= clk-exynos5433.o

obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos5433.o

obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o

obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o

obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-clkout.o