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Commit 3d7b2c60 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'davinci-for-v3.9/soc' of git://gitorious.org/linux-davinci/linux-davinci into next/soc 

From Sekhar Nori:
DaVinci SoC changes for v3.9

This pull request:

1) Fixes a bug with the way SPI devices were registered on DA850
2) Adds support for DSP clock and resetting the DSP on DA850
3) Fixes checkpatch issue with some existing files.

* tag 'davinci-for-v3.9/soc' of git://gitorious.org/linux-davinci/linux-davinci

:
  ARM: davinci: da850: add dsp clock definition
  ARM: davinci: psc: introduce reset API
  ARM: davinci: psc.c: change pr_warning() to pr_warn()
  ARM: davinci: devices-da8xx.c: change pr_warning() to pr_warn()
  ARM: davinci: da8xx_register_spi() should not register SPI board info

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0475e57f 09810a85

arch/arm/mach-davinci/board-da830-evm.c

+7 −2
Original line number Diff line number Diff line
@@ -652,8 +652,13 @@ static __init void da830_evm_init(void) 
	if (ret)

		pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);



	ret = da8xx_register_spi(0, da830evm_spi_info,

	ret = spi_register_board_info(da830evm_spi_info,

				      ARRAY_SIZE(da830evm_spi_info));

	if (ret)

		pr_warn("%s: spi info registration failed: %d\n", __func__,

			ret);



	ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info));

	if (ret)

		pr_warning("da830_evm_init: spi 0 registration failed: %d\n",

			   ret);

arch/arm/mach-davinci/board-da850-evm.c

+7 −2
Original line number Diff line number Diff line
@@ -1565,8 +1565,13 @@ static __init void da850_evm_init(void) 


	da850_vpif_init();



	ret = da8xx_register_spi(1, da850evm_spi_info,

	ret = spi_register_board_info(da850evm_spi_info,

				      ARRAY_SIZE(da850evm_spi_info));

	if (ret)

		pr_warn("%s: spi info registration failed: %d\n", __func__,

			ret);



	ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info));

	if (ret)

		pr_warning("da850_evm_init: spi 1 registration failed: %d\n",

				ret);

arch/arm/mach-davinci/board-mityomapl138.c

+7 −2
Original line number Diff line number Diff line
@@ -529,7 +529,12 @@ static void __init mityomapl138_init(void) 


	mityomapl138_setup_nand();



	ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,

	ret = spi_register_board_info(mityomapl138_spi_flash_info,

				      ARRAY_SIZE(mityomapl138_spi_flash_info));

	if (ret)

		pr_warn("spi info registration failed: %d\n", ret);



	ret = da8xx_register_spi_bus(1,

				     ARRAY_SIZE(mityomapl138_spi_flash_info));

	if (ret)

		pr_warning("spi 1 registration failed: %d\n", ret);

arch/arm/mach-davinci/clock.c

+38 −1
Original line number Diff line number Diff line
@@ -52,6 +52,40 @@ static void __clk_disable(struct clk *clk) 
		__clk_disable(clk->parent);

}



int davinci_clk_reset(struct clk *clk, bool reset)

{

	unsigned long flags;



	if (clk == NULL || IS_ERR(clk))

		return -EINVAL;



	spin_lock_irqsave(&clockfw_lock, flags);

	if (clk->flags & CLK_PSC)

		davinci_psc_reset(clk->gpsc, clk->lpsc, reset);

	spin_unlock_irqrestore(&clockfw_lock, flags);



	return 0;

}

EXPORT_SYMBOL(davinci_clk_reset);



int davinci_clk_reset_assert(struct clk *clk)

{

	if (clk == NULL || IS_ERR(clk) || !clk->reset)

		return -EINVAL;



	return clk->reset(clk, true);

}

EXPORT_SYMBOL(davinci_clk_reset_assert);



int davinci_clk_reset_deassert(struct clk *clk)

{

	if (clk == NULL || IS_ERR(clk) || !clk->reset)

		return -EINVAL;



	return clk->reset(clk, false);

}

EXPORT_SYMBOL(davinci_clk_reset_deassert);



int clk_enable(struct clk *clk)

{

	unsigned long flags;
@@ -576,6 +610,9 @@ int __init davinci_clk_init(struct clk_lookup *clocks) 
		if (clk->lpsc)

			clk->flags |= CLK_PSC;



		if (clk->flags & PSC_LRST)

			clk->reset = davinci_clk_reset;



		clk_register(clk);

		num_clocks++;

arch/arm/mach-davinci/clock.h

+3 −0
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ struct clk { 
	unsigned long (*recalc) (struct clk *);

	int (*set_rate) (struct clk *clk, unsigned long rate);

	int (*round_rate) (struct clk *clk, unsigned long rate);

	int (*reset) (struct clk *clk, bool reset);

};



/* Clock flags: SoC-specific flags start at BIT(16) */
@@ -112,6 +113,7 @@ struct clk { 
#define PRE_PLL			BIT(4) /* source is before PLL mult/div */

#define PSC_SWRSTDISABLE	BIT(5) /* Disable state is SwRstDisable */

#define PSC_FORCE		BIT(6) /* Force module state transtition */

#define PSC_LRST		BIT(8) /* Use local reset on enable/disable */



#define CLK(dev, con, ck) 	\

	{			\
@@ -126,6 +128,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);

int davinci_set_refclk_rate(unsigned long rate);

int davinci_simple_set_rate(struct clk *clk, unsigned long rate);

int davinci_clk_reset(struct clk *clk, bool reset);



extern struct platform_device davinci_wdt_device;

extern void davinci_watchdog_reset(struct platform_device *);