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Commit 3d6437b3 authored by Mike Frysinger's avatar Mike Frysinger
Browse files

Blackfin: punt short SPI MMR bit names 



Now that the common header defines everything and the SPI drivers are
using it, we can drop these duplicated global namespace polluters.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent d4429f60

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+0 −45
Original line number Diff line number Diff line
@@ -748,51 +748,6 @@ 
#define FFE			0x20		/* Force Framing Error On Transmit	*/





/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/

/* SPI_CTL Masks																	*/

#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/

#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/

#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/

#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/

#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/

#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/

#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/

#define PSSE		0x0010		/* Slave-Select Input Enable						*/

#define EMISO		0x0020		/* Enable MISO As Output							*/

#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/

#define LSBF		0x0200		/* LSB First										*/

#define CPHA		0x0400		/* Clock Phase										*/

#define CPOL		0x0800		/* Clock Polarity									*/

#define MSTR		0x1000		/* Master/Slave*									*/

#define WOM			0x2000		/* Write Open Drain Master							*/

#define SPE			0x4000		/* SPI Enable										*/



/* SPI_FLG Masks																	*/

#define FLS1		0x0002		/* Enables SPI_FLOUT1 as SPI Slave-Select Output	*/

#define FLS2		0x0004		/* Enables SPI_FLOUT2 as SPI Slave-Select Output	*/

#define FLS3		0x0008		/* Enables SPI_FLOUT3 as SPI Slave-Select Output	*/

#define FLS4		0x0010		/* Enables SPI_FLOUT4 as SPI Slave-Select Output	*/

#define FLS5		0x0020		/* Enables SPI_FLOUT5 as SPI Slave-Select Output	*/

#define FLS6		0x0040		/* Enables SPI_FLOUT6 as SPI Slave-Select Output	*/

#define FLS7		0x0080		/* Enables SPI_FLOUT7 as SPI Slave-Select Output	*/

#define FLG1		0xFDFF		/* Activates SPI_FLOUT1 							*/

#define FLG2		0xFBFF		/* Activates SPI_FLOUT2								*/

#define FLG3		0xF7FF		/* Activates SPI_FLOUT3								*/

#define FLG4		0xEFFF		/* Activates SPI_FLOUT4								*/

#define FLG5		0xDFFF		/* Activates SPI_FLOUT5								*/

#define FLG6		0xBFFF		/* Activates SPI_FLOUT6								*/

#define FLG7		0x7FFF		/* Activates SPI_FLOUT7								*/



/* SPI_STAT Masks																				*/

#define SPIF		0x0001		/* SPI Finished (Single-Word Transfer Complete)					*/

#define MODF		0x0002		/* Mode Fault Error (Another Device Tried To Become Master)		*/

#define TXE			0x0004		/* Transmission Error (Data Sent With No New Data In TDBR)		*/

#define TXS			0x0008		/* SPI_TDBR Data Buffer Status (Full/Empty*)					*/

#define RBSY		0x0010		/* Receive Error (Data Received With RDBR Full)					*/

#define RXS			0x0020		/* SPI_RDBR Data Buffer Status (Full/Empty*)					*/

#define TXCOL		0x0040		/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/





/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/

/* TIMER_ENABLE Masks													*/

#define TIMEN0			0x0001		/* Enable Timer 0					*/

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

+0 −45
Original line number Diff line number Diff line
@@ -749,51 +749,6 @@ 
#define FFE			0x20		/* Force Framing Error On Transmit	*/





/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/

/* SPI_CTL Masks																	*/

#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/

#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/

#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/

#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/

#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/

#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/

#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/

#define PSSE		0x0010		/* Slave-Select Input Enable						*/

#define EMISO		0x0020		/* Enable MISO As Output							*/

#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/

#define LSBF		0x0200		/* LSB First										*/

#define CPHA		0x0400		/* Clock Phase										*/

#define CPOL		0x0800		/* Clock Polarity									*/

#define MSTR		0x1000		/* Master/Slave*									*/

#define WOM			0x2000		/* Write Open Drain Master							*/

#define SPE			0x4000		/* SPI Enable										*/



/* SPI_FLG Masks																	*/

#define FLS1		0x0002		/* Enables SPI_FLOUT1 as SPI Slave-Select Output	*/

#define FLS2		0x0004		/* Enables SPI_FLOUT2 as SPI Slave-Select Output	*/

#define FLS3		0x0008		/* Enables SPI_FLOUT3 as SPI Slave-Select Output	*/

#define FLS4		0x0010		/* Enables SPI_FLOUT4 as SPI Slave-Select Output	*/

#define FLS5		0x0020		/* Enables SPI_FLOUT5 as SPI Slave-Select Output	*/

#define FLS6		0x0040		/* Enables SPI_FLOUT6 as SPI Slave-Select Output	*/

#define FLS7		0x0080		/* Enables SPI_FLOUT7 as SPI Slave-Select Output	*/

#define FLG1		0xFDFF		/* Activates SPI_FLOUT1 							*/

#define FLG2		0xFBFF		/* Activates SPI_FLOUT2								*/

#define FLG3		0xF7FF		/* Activates SPI_FLOUT3								*/

#define FLG4		0xEFFF		/* Activates SPI_FLOUT4								*/

#define FLG5		0xDFFF		/* Activates SPI_FLOUT5								*/

#define FLG6		0xBFFF		/* Activates SPI_FLOUT6								*/

#define FLG7		0x7FFF		/* Activates SPI_FLOUT7								*/



/* SPI_STAT Masks																				*/

#define SPIF		0x0001		/* SPI Finished (Single-Word Transfer Complete)					*/

#define MODF		0x0002		/* Mode Fault Error (Another Device Tried To Become Master)		*/

#define TXE			0x0004		/* Transmission Error (Data Sent With No New Data In TDBR)		*/

#define TXS			0x0008		/* SPI_TDBR Data Buffer Status (Full/Empty*)					*/

#define RBSY		0x0010		/* Receive Error (Data Received With RDBR Full)					*/

#define RXS			0x0020		/* SPI_RDBR Data Buffer Status (Full/Empty*)					*/

#define TXCOL		0x0040		/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/





/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/

/* TIMER_ENABLE Masks													*/

#define TIMEN0			0x0001		/* Enable Timer 0					*/

arch/blackfin/mach-bf533/include/mach/defBF532.h

+0 −70
Original line number Diff line number Diff line
@@ -681,76 +681,6 @@ 
#define PF14_P        14

#define PF15_P        15



/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */



/* SPI_CTL Masks */

#define TIMOD                  0x00000003	/* Transfer initiation mode and interrupt generation */

#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/

#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/

#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/

#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/

#define SZ                     0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty. */

#define GM                     0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */

#define PSSE                   0x00000010	/* Enable (=1) Slave-Select input for Master. */

#define EMISO                  0x00000020	/* Enable (=1) MISO pin as an output. */

#define SIZE                   0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */

#define LSBF                   0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */

#define CPHA                   0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */

#define CPOL                   0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */

#define MSTR                   0x00001000	/* Configures SPI as master (=1) or slave (=0) */

#define WOM                    0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */

#define SPE                    0x00004000	/* SPI module enable (=1), disable (=0) */



/* SPI_FLG Masks */

#define FLS1                   0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */

#define FLS2                   0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */

#define FLS3                   0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */

#define FLS4                   0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */

#define FLS5                   0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */

#define FLS6                   0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */

#define FLS7                   0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */

#define FLG1                   0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */

#define FLG2                   0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */

#define FLG3                   0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */

#define FLG4                   0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */

#define FLG5                   0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */

#define FLG6                   0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */

#define FLG7                   0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */



/* SPI_FLG Bit Positions */

#define FLS1_P                 0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */

#define FLS2_P                 0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */

#define FLS3_P                 0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */

#define FLS4_P                 0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */

#define FLS5_P                 0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */

#define FLS6_P                 0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */

#define FLS7_P                 0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */

#define FLG1_P                 0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */

#define FLG2_P                 0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */

#define FLG3_P                 0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */

#define FLG4_P                 0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */

#define FLG5_P                 0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */

#define FLG6_P                 0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */

#define FLG7_P                 0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */



/* SPI_STAT Masks */

#define SPIF                   0x00000001	/* Set (=1) when SPI single-word transfer complete */

#define MODF                   0x00000002	/* Set (=1) in a master device when some other device tries to become master */

#define TXE                    0x00000004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */

#define TXS                    0x00000008	/* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */

#define RBSY                   0x00000010	/* Set (=1) when data is received with RDBR full */

#define RXS                    0x00000020	/* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */

#define TXCOL                  0x00000040	/* When set (=1), corrupt data may have been transmitted  */



/* SPIx_FLG Masks																	*/

#define FLG1E	0xFDFF		/* Activates SPI_FLOUT1 							*/

#define FLG2E	0xFBFF		/* Activates SPI_FLOUT2								*/

#define FLG3E	0xF7FF		/* Activates SPI_FLOUT3								*/

#define FLG4E	0xEFFF		/* Activates SPI_FLOUT4								*/

#define FLG5E	0xDFFF		/* Activates SPI_FLOUT5								*/

#define FLG6E	0xBFFF		/* Activates SPI_FLOUT6								*/

#define FLG7E	0x7FFF		/* Activates SPI_FLOUT7								*/



/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */



/* AMGCTL Masks */

arch/blackfin/mach-bf537/include/mach/defBF534.h

+0 −44
Original line number Diff line number Diff line
@@ -1071,50 +1071,6 @@ 
#define FPE			0x10	/* Force Parity Error On Transmit       */

#define FFE			0x20	/* Force Framing Error On Transmit      */



/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/

/* SPI_CTL Masks																	*/

#define	TIMOD		0x0003	/* Transfer Initiate Mode                                                       */

#define RDBR_CORE	0x0000	/*              RDBR Read Initiates, IRQ When RDBR Full         */

#define	TDBR_CORE	0x0001	/*              TDBR Write Initiates, IRQ When TDBR Empty       */

#define RDBR_DMA	0x0002	/*              DMA Read, DMA Until FIFO Empty                          */

#define TDBR_DMA	0x0003	/*              DMA Write, DMA Until FIFO Full                          */

#define SZ			0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*)         */

#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*)        */

#define PSSE		0x0010	/* Slave-Select Input Enable                                            */

#define EMISO		0x0020	/* Enable MISO As Output                                                        */

#define SIZE		0x0100	/* Size of Words (16/8* Bits)                                           */

#define LSBF		0x0200	/* LSB First                                                                            */

#define CPHA		0x0400	/* Clock Phase                                                                          */

#define CPOL		0x0800	/* Clock Polarity                                                                       */

#define MSTR		0x1000	/* Master/Slave*                                                                        */

#define WOM			0x2000	/* Write Open Drain Master                                                      */

#define SPE			0x4000	/* SPI Enable                                                                           */



/* SPI_FLG Masks																	*/

#define FLS1		0x0002	/* Enables SPI_FLOUT1 as SPI Slave-Select Output        */

#define FLS2		0x0004	/* Enables SPI_FLOUT2 as SPI Slave-Select Output        */

#define FLS3		0x0008	/* Enables SPI_FLOUT3 as SPI Slave-Select Output        */

#define FLS4		0x0010	/* Enables SPI_FLOUT4 as SPI Slave-Select Output        */

#define FLS5		0x0020	/* Enables SPI_FLOUT5 as SPI Slave-Select Output        */

#define FLS6		0x0040	/* Enables SPI_FLOUT6 as SPI Slave-Select Output        */

#define FLS7		0x0080	/* Enables SPI_FLOUT7 as SPI Slave-Select Output        */

#define FLG1		0xFDFF	/* Activates SPI_FLOUT1                                                         */

#define FLG2		0xFBFF	/* Activates SPI_FLOUT2                                                         */

#define FLG3		0xF7FF	/* Activates SPI_FLOUT3                                                         */

#define FLG4		0xEFFF	/* Activates SPI_FLOUT4                                                         */

#define FLG5		0xDFFF	/* Activates SPI_FLOUT5                                                         */

#define FLG6		0xBFFF	/* Activates SPI_FLOUT6                                                         */

#define FLG7		0x7FFF	/* Activates SPI_FLOUT7                                                         */



/* SPI_STAT Masks																				*/

#define SPIF		0x0001	/* SPI Finished (Single-Word Transfer Complete)                                 */

#define MODF		0x0002	/* Mode Fault Error (Another Device Tried To Become Master)             */

#define TXE			0x0004	/* Transmission Error (Data Sent With No New Data In TDBR)              */

#define TXS			0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */

#define RBSY		0x0010	/* Receive Error (Data Received With RDBR Full)                                 */

#define RXS			0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */

#define TXCOL		0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent)   */



/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/

/* TIMER_ENABLE Masks													*/

#define TIMEN0			0x0001	/* Enable Timer 0                                       */

arch/blackfin/mach-bf538/include/mach/defBF539.h

+0 −72
Original line number Diff line number Diff line
@@ -1894,78 +1894,6 @@ 
#define	PE14_P	0xE

#define	PE15_P	0xF





/* ***********	SERIAL PERIPHERAL INTERFACE (SPI) MASKS	 **************** */

/* SPIx_CTL Masks */

#define	TIMOD		0x0003		/* Transfer Initiate Mode */

#define	RDBR_CORE	0x0000		/*		RDBR Read Initiates, IRQ When RDBR Full */

#define	TDBR_CORE	0x0001		/*		TDBR Write Initiates, IRQ When TDBR Empty */

#define	RDBR_DMA	0x0002		/*		DMA Read, DMA Until FIFO Empty */

#define	TDBR_DMA	0x0003		/*		DMA Write, DMA Until FIFO Full */

#define	SZ			0x0004		/* Send	Zero (When TDBR	Empty, Send Zero/Last*) */

#define	GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*) */

#define	PSSE		0x0010		/* Slave-Select	Input Enable */

#define	EMISO		0x0020		/* Enable MISO As Output */

#define	SIZE		0x0100		/* Size	of Words (16/8*	Bits) */

#define	LSBF		0x0200		/* LSB First			 */

#define	CPHA		0x0400		/* Clock Phase			 */

#define	CPOL		0x0800		/* Clock Polarity		 */

#define	MSTR		0x1000		/* Master/Slave*		 */

#define	WOM			0x2000		/* Write Open Drain Master */

#define	SPE			0x4000		/* SPI Enable			 */



/* SPIx_FLG Masks */

#define	FLS1	0x0002	/* Enables (=1)	SPI_FLOUT1 as flag output for SPI Slave-select */

#define	FLS2	0x0004	/* Enables (=1)	SPI_FLOUT2 as flag output for SPI Slave-select */

#define	FLS3	0x0008	/* Enables (=1)	SPI_FLOUT3 as flag output for SPI Slave-select */

#define	FLS4	0x0010	/* Enables (=1)	SPI_FLOUT4 as flag output for SPI Slave-select */

#define	FLS5	0x0020	/* Enables (=1)	SPI_FLOUT5 as flag output for SPI Slave-select */

#define	FLS6	0x0040	/* Enables (=1)	SPI_FLOUT6 as flag output for SPI Slave-select */

#define	FLS7	0x0080	/* Enables (=1)	SPI_FLOUT7 as flag output for SPI Slave-select */



#define	FLG1	0x0200	/* Activates (=0) SPI_FLOUT1 as	flag output for	SPI Slave-select  */

#define	FLG2	0x0400	/* Activates (=0) SPI_FLOUT2 as	flag output for	SPI Slave-select */

#define	FLG3	0x0800	/* Activates (=0) SPI_FLOUT3 as	flag output for	SPI Slave-select  */

#define	FLG4	0x1000	/* Activates (=0) SPI_FLOUT4 as	flag output for	SPI Slave-select  */

#define	FLG5	0x2000	/* Activates (=0) SPI_FLOUT5 as	flag output for	SPI Slave-select  */

#define	FLG6	0x4000	/* Activates (=0) SPI_FLOUT6 as	flag output for	SPI Slave-select  */

#define	FLG7	0x8000	/* Activates (=0) SPI_FLOUT7 as	flag output for	SPI Slave-select */



/* SPIx_FLG Bit	Positions */

#define	FLS1_P	0x0001	/* Enables (=1)	SPI_FLOUT1 as flag output for SPI Slave-select */

#define	FLS2_P	0x0002	/* Enables (=1)	SPI_FLOUT2 as flag output for SPI Slave-select */

#define	FLS3_P	0x0003	/* Enables (=1)	SPI_FLOUT3 as flag output for SPI Slave-select */

#define	FLS4_P	0x0004	/* Enables (=1)	SPI_FLOUT4 as flag output for SPI Slave-select */

#define	FLS5_P	0x0005	/* Enables (=1)	SPI_FLOUT5 as flag output for SPI Slave-select */

#define	FLS6_P	0x0006	/* Enables (=1)	SPI_FLOUT6 as flag output for SPI Slave-select */

#define	FLS7_P	0x0007	/* Enables (=1)	SPI_FLOUT7 as flag output for SPI Slave-select */

#define	FLG1_P	0x0009	/* Activates (=0) SPI_FLOUT1 as	flag output for	SPI Slave-select  */

#define	FLG2_P	0x000A	/* Activates (=0) SPI_FLOUT2 as	flag output for	SPI Slave-select */

#define	FLG3_P	0x000B	/* Activates (=0) SPI_FLOUT3 as	flag output for	SPI Slave-select  */

#define	FLG4_P	0x000C	/* Activates (=0) SPI_FLOUT4 as	flag output for	SPI Slave-select  */

#define	FLG5_P	0x000D	/* Activates (=0) SPI_FLOUT5 as	flag output for	SPI Slave-select  */

#define	FLG6_P	0x000E	/* Activates (=0) SPI_FLOUT6 as	flag output for	SPI Slave-select  */

#define	FLG7_P	0x000F	/* Activates (=0) SPI_FLOUT7 as	flag output for	SPI Slave-select */



/* SPIx_STAT Masks */

#define	SPIF	0x0001	/* Set (=1) when SPI single-word transfer complete */

#define	MODF	0x0002	/* Set (=1) in a master	device when some other device tries to become master */

#define	TXE		0x0004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */

#define	TXS		0x0008	/* SPI_TDBR Data Buffer	Status (0=Empty, 1=Full) */

#define	RBSY	0x0010	/* Set (=1) when data is received with RDBR full */

#define	RXS		0x0020	/* SPI_RDBR Data Buffer	Status (0=Empty, 1=Full)  */

#define	TXCOL	0x0040	/* When	set (=1), corrupt data may have	been transmitted  */



/* SPIx_FLG Masks										 */

#define	FLG1E	0xFDFF		/* Activates SPI_FLOUT1	 */

#define	FLG2E	0xFBFF		/* Activates SPI_FLOUT2	 */

#define	FLG3E	0xF7FF		/* Activates SPI_FLOUT3	 */

#define	FLG4E	0xEFFF		/* Activates SPI_FLOUT4	 */

#define	FLG5E	0xDFFF		/* Activates SPI_FLOUT5	 */

#define	FLG6E	0xBFFF		/* Activates SPI_FLOUT6	 */

#define	FLG7E	0x7FFF		/* Activates SPI_FLOUT7	 */





/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS	************* */

/* EBIU_AMGCTL Masks */

#define	AMCKEN		0x0001	/* Enable CLKOUT */