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Commit 3d56f89f authored by Dhaval Patel's avatar Dhaval Patel
Browse files

drm/msm: fix sde rsc vsync and dynamic mode debug support 



Fix timer configuration and vsync configuration on SDE
rsc for vsync and mode control dynamic debugging.

Change-Id: I561366ff71f934b6af69290e643b7a7b0bda96a8
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 56c0a94b

drivers/gpu/drm/msm/sde_rsc.c

+38 −40
Original line number Diff line number Diff line
@@ -780,14 +780,15 @@ static ssize_t _sde_debugfs_mode_ctrl_write(struct file *file, 
			const char __user *p, size_t count, loff_t *ppos)

{

	struct sde_rsc_priv *rsc = file->private_data;

	char *input, *mode;

	u32 mode0_state = 0, mode1_state = 0, mode2_state = 0;

	char *input;

	u32 mode_state = 0;

	int rc;



	if (!rsc || !rsc->hw_ops.mode_ctrl)

	if (!rsc || !rsc->hw_ops.mode_ctrl || !count ||

					count > MAX_COUNT_SIZE_SUPPORTED)

		return 0;



	input = kmalloc(count, GFP_KERNEL);

	input = kmalloc(count + 1, GFP_KERNEL);

	if (!input)

		return -ENOMEM;
@@ -795,43 +796,35 @@ static ssize_t _sde_debugfs_mode_ctrl_write(struct file *file, 
		kfree(input);

		return -EFAULT;

	}

	input[count - 1] = '\0';

	input[count] = '\0';



	mutex_lock(&rsc->client_lock);

	rc = sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, true);

	if (rc)

		goto clk_enable_fail;



	mode = strnstr(input, "mode0=", strlen("mode0="));

	if (mode) {

		mode0_state = mode[0] - '0';

		mode0_state &= BIT(0);

		rsc->hw_ops.mode_ctrl(rsc, MODE0_UPDATE, NULL, 0, mode0_state);

	rc = kstrtoint(input, 0, &mode_state);

	if (rc) {

		pr_err("mode_state: int conversion failed rc:%d\n", rc);

		goto end;

	}



	mode = strnstr(input, "mode1=", strlen("mode1="));

	if (mode) {

		mode1_state = mode[0] - '0';

		mode1_state &= BIT(0);

		rsc->hw_ops.mode_ctrl(rsc, MODE1_UPDATE, NULL, 0, mode1_state);

	pr_debug("mode_state: %d\n", mode_state);

	mode_state &= 0x7;

	if (mode_state != ALL_MODES_DISABLED &&

			mode_state != ALL_MODES_ENABLED &&

			mode_state != ONLY_MODE_0_ENABLED &&

			mode_state != ONLY_MODE_0_1_ENABLED) {

		pr_err("invalid mode:%d combination\n", mode_state);

		goto end;

	}



	mode = strnstr(input, "mode2=", strlen("mode2="));

	if (mode) {

		mode2_state = mode[0] - '0';

		mode2_state &= BIT(0);

		rsc->hw_ops.mode_ctrl(rsc, MODE2_UPDATE, NULL, 0, mode2_state);

	}

	mutex_lock(&rsc->client_lock);

	rc = sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, true);

	if (rc)

		goto clk_enable_fail;



end:

	rsc->hw_ops.mode_ctrl(rsc, MODE_UPDATE, NULL, 0, mode_state);

	sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, false);



clk_enable_fail:

	mutex_unlock(&rsc->client_lock);



	pr_info("req: mode0:%d mode1:%d mode2:%d\n", mode0_state, mode1_state,

								mode2_state);

end:

	kfree(input);

	return count;

}
@@ -879,14 +872,15 @@ static ssize_t _sde_debugfs_vsync_mode_write(struct file *file, 
			const char __user *p, size_t count, loff_t *ppos)

{

	struct sde_rsc_priv *rsc = file->private_data;

	char *input, *vsync_mode;

	char *input;

	u32 vsync_state = 0;

	int rc;



	if (!rsc || !rsc->hw_ops.hw_vsync)

	if (!rsc || !rsc->hw_ops.hw_vsync || !count ||

				count > MAX_COUNT_SIZE_SUPPORTED)

		return 0;



	input = kmalloc(count, GFP_KERNEL);

	input = kmalloc(count + 1, GFP_KERNEL);

	if (!input)

		return -ENOMEM;
@@ -894,18 +888,21 @@ static ssize_t _sde_debugfs_vsync_mode_write(struct file *file, 
		kfree(input);

		return -EFAULT;

	}

	input[count - 1] = '\0';

	input[count] = '\0';



	vsync_mode = strnstr(input, "vsync_mode=", strlen("vsync_mode="));

	if (vsync_mode) {

		vsync_state = vsync_mode[0] - '0';

		vsync_state &= 0x7;

	rc = kstrtoint(input, 0, &vsync_state);

	if (rc) {

		pr_err("vsync_state: int conversion failed rc:%d\n", rc);

		goto end;

	}



	pr_debug("vsync_state: %d\n", vsync_state);

	vsync_state &= 0x7;



	mutex_lock(&rsc->client_lock);

	rc = sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, true);

	if (rc)

		goto end;

		goto clk_en_fail;



	if (vsync_state)

		rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL,
@@ -915,8 +912,9 @@ static ssize_t _sde_debugfs_vsync_mode_write(struct file *file, 


	sde_rsc_clk_enable(&rsc->phandle, rsc->pclient, false);



end:

clk_en_fail:

	mutex_unlock(&rsc->client_lock);

end:

	kfree(input);

	return count;

}

drivers/gpu/drm/msm/sde_rsc_hw.c

+13 −22
Original line number Diff line number Diff line
@@ -572,7 +572,7 @@ int rsc_hw_init(struct sde_rsc_priv *rsc) 
}



int rsc_hw_mode_ctrl(struct sde_rsc_priv *rsc, enum rsc_mode_req request,

		char *buffer, int buffer_size, bool mode)

		char *buffer, int buffer_size, u32 mode)

{

	u32 blen = 0;

	u32 slot_time;
@@ -588,28 +588,19 @@ int rsc_hw_mode_ctrl(struct sde_rsc_priv *rsc, enum rsc_mode_req request, 
			rsc->debug_mode));

		break;



	case MODE0_UPDATE:

		slot_time = mode ? rsc->timer_config.rsc_time_slot_0_ns :

				rsc->timer_config.rsc_time_slot_2_ns;

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_1_DRV0,

						slot_time, rsc->debug_mode);

		slot_time = mode ? rsc->timer_config.rsc_time_slot_1_ns :

	case MODE_UPDATE:

		slot_time = mode & BIT(0) ? 0x0 :

					rsc->timer_config.rsc_time_slot_2_ns;

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_2_DRV0,

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_0_DRV0,

						slot_time, rsc->debug_mode);

		rsc->power_collapse_block = mode;

		break;



	case MODE1_UPDATE:

		slot_time = mode ? rsc->timer_config.rsc_time_slot_1_ns :

		slot_time = mode & BIT(1) ?

			rsc->timer_config.rsc_time_slot_0_ns :

				rsc->timer_config.rsc_time_slot_2_ns;

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_2_DRV0,

		dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_TIME_SLOT_TABLE_1_DRV0,

						slot_time, rsc->debug_mode);

		rsc->power_collapse_block = mode;

		break;



	case MODE2_UPDATE:

		rsc->power_collapse_block = mode;

		rsc->power_collapse_block = !(mode & BIT(2));

		break;



	default:
@@ -673,7 +664,7 @@ int rsc_hw_vsync(struct sde_rsc_priv *rsc, enum rsc_vsync_req request, 
			return blen;



		blen = snprintf(buffer, buffer_size - blen, "vsync0:0x%x\n",

			 dss_reg_r(&rsc->drv_io,

			 dss_reg_r(&rsc->wrapper_io,

				SDE_RSCC_WRAPPER_VSYNC_TIMESTAMP0,

				rsc->debug_mode));

		if (blen >= buffer_size)
@@ -681,15 +672,15 @@ int rsc_hw_vsync(struct sde_rsc_priv *rsc, enum rsc_vsync_req request, 


		blen += snprintf(buffer + blen, buffer_size - blen,

			"vsync1:0x%x\n",

			 dss_reg_r(&rsc->drv_io,

			 dss_reg_r(&rsc->wrapper_io,

				SDE_RSCC_WRAPPER_VSYNC_TIMESTAMP1,

				rsc->debug_mode));

		break;



	case VSYNC_ENABLE:

		reg = BIT(8) | BIT(9) | ((mode & 0x7) < 10);

		reg = BIT(8) | ((mode & 0x7) < 10);

		dss_reg_w(&rsc->wrapper_io, SDE_RSCC_WRAPPER_DEBUG_BUS,

					mode, rsc->debug_mode);

					reg, rsc->debug_mode);

		break;



	case VSYNC_DISABLE:

drivers/gpu/drm/msm/sde_rsc_priv.h

+14 −7
Original line number Diff line number Diff line
@@ -25,20 +25,27 @@ 


#define MAX_RSC_COUNT		5



#define ALL_MODES_DISABLED	0x0

#define ONLY_MODE_0_ENABLED	0x1

#define ONLY_MODE_0_1_ENABLED	0x3

#define ALL_MODES_ENABLED	0x7



#define MAX_COUNT_SIZE_SUPPORTED	128



struct sde_rsc_priv;



/**

 * rsc_mode_req: sde rsc mode request information

 * MODE_READ: read vsync status

 * MODE0_UPDATE: mode0 status , this should be 0x0

 * MODE1_UPDATE: mode1 status , this should be 0x1

 * MODE2_UPDATE: mode2 status , this should be 0x2

 * MODE_UPDATE: mode timeslot update

 *            0x0: all modes are disabled.

 *            0x1: Mode-0 is enabled and other two modes are disabled.

 *            0x3: Mode-0 & Mode-1 are enabled and mode-2 is disabled.

 *            0x7: all modes are enabled.

 */

enum rsc_mode_req {

	MODE_READ,

	MODE0_UPDATE = 0x1,

	MODE1_UPDATE = 0x2,

	MODE2_UPDATE = 0x3,

	MODE_UPDATE = 0x1,

};



/**
@@ -78,7 +85,7 @@ struct sde_rsc_hw_ops { 
	int (*state_update)(struct sde_rsc_priv *rsc, enum sde_rsc_state state);

	int (*debug_show)(struct seq_file *s, struct sde_rsc_priv *rsc);

	int (*mode_ctrl)(struct sde_rsc_priv *rsc, enum rsc_mode_req request,

		char *buffer, int buffer_size, bool mode);

		char *buffer, int buffer_size, u32 mode);

};



/**