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Commit 3c7066bc authored by Francisco Jerez's avatar Francisco Jerez Committed by Ben Skeggs
Browse files

drm/nouveau: Add some PFB register defines. 



Also collect all the PFB registers in a single place and remove some
duplicated definitions.

Signed-off-by: default avatarFrancisco Jerez <currojerez@riseup.net>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 20b24005

drivers/gpu/drm/nouveau/nouveau_bios.c

+11 −11
Original line number Diff line number Diff line
@@ -2129,10 +2129,10 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 
	 * This also has probably been done in the scripts, but an mmio trace of

	 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)

	 */

	bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1);

	bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);



	/* write back the saved configuration value */

	bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);

	bios_wr32(bios, NV04_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);



	return 1;

}
@@ -2209,14 +2209,14 @@ init_configure_mem(struct nvbios *bios, uint16_t offset, 
	     reg = ROM32(bios->data[seqtbloffs += 4])) {



		switch (reg) {

		case NV_PFB_PRE:

			data = NV_PFB_PRE_CMD_PRECHARGE;

		case NV04_PFB_PRE:

			data = NV04_PFB_PRE_CMD_PRECHARGE;

			break;

		case NV_PFB_PAD:

			data = NV_PFB_PAD_CKE_NORMAL;

		case NV04_PFB_PAD:

			data = NV04_PFB_PAD_CKE_NORMAL;

			break;

		case NV_PFB_REF:

			data = NV_PFB_REF_CMD_REFRESH;

		case NV04_PFB_REF:

			data = NV04_PFB_REF_CMD_REFRESH;

			break;

		default:

			data = ROM32(bios->data[meminitdata]);
@@ -2418,7 +2418,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset, 
	 * offset + 1  (8 bit): mask

	 * offset + 2  (8 bit): cmpval

	 *

	 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval".

	 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".

	 * If condition not met skip subsequent opcodes until condition is

	 * inverted (INIT_NOT), or we hit INIT_RESUME

	 */
@@ -2430,7 +2430,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset, 
	if (!iexec->execute)

		return 3;



	data = bios_rd32(bios, NV_PFB_BOOT_0) & mask;

	data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;



	BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",

		offset, data, cmpval);
@@ -6343,7 +6343,7 @@ nouveau_bios_init(struct drm_device *dev) 


	/* these will need remembering across a suspend */

	saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);

	bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0);

	bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV04_PFB_CFG0);



	/* init script execution disabled */

	bios->execute = false;

drivers/gpu/drm/nouveau/nouveau_calc.c

+2 −2
Original line number Diff line number Diff line
@@ -200,7 +200,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 
	struct nv_sim_state sim_data;

	int MClk = nouveau_hw_get_clock(dev, MPLL);

	int NVClk = nouveau_hw_get_clock(dev, NVPLL);

	uint32_t cfg1 = nvReadFB(dev, NV_PFB_CFG1);

	uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1);



	sim_data.pclk_khz = VClk;

	sim_data.mclk_khz = MClk;
@@ -218,7 +218,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 
		sim_data.mem_latency = 3;

		sim_data.mem_page_miss = 10;

	} else {

		sim_data.memory_type = nvReadFB(dev, NV_PFB_CFG0) & 0x1;

		sim_data.memory_type = nvReadFB(dev, NV04_PFB_CFG0) & 0x1;

		sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;

		sim_data.mem_latency = cfg1 & 0xf;

		sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);

drivers/gpu/drm/nouveau/nouveau_mem.c

+9 −9
Original line number Diff line number Diff line
@@ -260,19 +260,19 @@ nouveau_mem_close(struct drm_device *dev) 
static uint32_t

nouveau_mem_detect_nv04(struct drm_device *dev)

{

	uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);

	uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);



	if (boot0 & 0x00000100)

		return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;



	switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {

	case NV04_BOOT_0_RAM_AMOUNT_32MB:

	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {

	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:

		return 32 * 1024 * 1024;

	case NV04_BOOT_0_RAM_AMOUNT_16MB:

	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:

		return 16 * 1024 * 1024;

	case NV04_BOOT_0_RAM_AMOUNT_8MB:

	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:

		return 8 * 1024 * 1024;

	case NV04_BOOT_0_RAM_AMOUNT_4MB:

	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:

		return 4 * 1024 * 1024;

	}
@@ -318,10 +318,10 @@ nouveau_mem_detect(struct drm_device *dev) 
		dev_priv->vram_size = nouveau_mem_detect_nforce(dev);

	} else

	if (dev_priv->card_type < NV_50) {

		dev_priv->vram_size  = nv_rd32(dev, NV04_FIFO_DATA);

		dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;

		dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);

		dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;

	} else {

		dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);

		dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);

		dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;

		dev_priv->vram_size &= 0xffffffff00ll;

		if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {

drivers/gpu/drm/nouveau/nouveau_reg.h

+59 −31
Original line number Diff line number Diff line 


#define NV04_PFB_BOOT_0						0x00100000

#	define NV04_PFB_BOOT_0_RAM_AMOUNT			0x00000003

#	define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB			0x00000000

#	define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB			0x00000001

#	define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB			0x00000002

#	define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB			0x00000003

#	define NV04_PFB_BOOT_0_RAM_WIDTH_128			0x00000004

#	define NV04_PFB_BOOT_0_RAM_TYPE				0x00000028

#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT		0x00000000

#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT		0x00000008

#	define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK	0x00000010

#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT		0x00000018

#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT		0x00000020

#	define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16		0x00000028

#	define NV04_PFB_BOOT_0_UMA_ENABLE			0x00000100

#	define NV04_PFB_BOOT_0_UMA_SIZE				0x0000f000

#define NV04_PFB_DEBUG_0					0x00100080

#	define NV04_PFB_DEBUG_0_PAGE_MODE			0x00000001

#	define NV04_PFB_DEBUG_0_REFRESH_OFF			0x00000010

#	define NV04_PFB_DEBUG_0_REFRESH_COUNTX64		0x00003f00

#	define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK		0x00004000

#	define NV04_PFB_DEBUG_0_SAFE_MODE			0x00008000

#	define NV04_PFB_DEBUG_0_ALOM_ENABLE			0x00010000

#	define NV04_PFB_DEBUG_0_CASOE				0x00100000

#	define NV04_PFB_DEBUG_0_CKE_INVERT			0x10000000

#	define NV04_PFB_DEBUG_0_REFINC				0x20000000

#	define NV04_PFB_DEBUG_0_SAVE_POWER_OFF			0x40000000

#define NV04_PFB_CFG0						0x00100200

#	define NV04_PFB_CFG0_SCRAMBLE				0x20000000

#define NV04_PFB_CFG1						0x00100204

#define NV04_PFB_FIFO_DATA					0x0010020c

#	define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK		0xfff00000

#	define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT		20

#define NV10_PFB_REFCTRL					0x00100210

#	define NV10_PFB_REFCTRL_VALID_1				(1 << 31)

#define NV04_PFB_PAD						0x0010021c

#	define NV04_PFB_PAD_CKE_NORMAL				(1 << 0)

#define NV10_PFB_TILE(i)                              (0x00100240 + (i*16))

#define NV10_PFB_TILE__SIZE					8

#define NV10_PFB_TLIMIT(i)                            (0x00100244 + (i*16))

#define NV10_PFB_TSIZE(i)                             (0x00100248 + (i*16))

#define NV10_PFB_TSTATUS(i)                           (0x0010024c + (i*16))

#define NV04_PFB_REF						0x001002d0

#	define NV04_PFB_REF_CMD_REFRESH				(1 << 0)

#define NV04_PFB_PRE						0x001002d4

#	define NV04_PFB_PRE_CMD_PRECHARGE			(1 << 0)

#define NV10_PFB_CLOSE_PAGE2					0x0010033c

#define NV04_PFB_SCRAMBLE(i)                         (0x00100400 + 4 * (i))

#define NV40_PFB_TILE(i)                              (0x00100600 + (i*16))

#define NV40_PFB_TILE__SIZE_0					12

#define NV40_PFB_TILE__SIZE_1					15

#define NV40_PFB_TLIMIT(i)                            (0x00100604 + (i*16))

#define NV40_PFB_TSIZE(i)                             (0x00100608 + (i*16))

#define NV40_PFB_TSTATUS(i)                           (0x0010060c + (i*16))

#define NV40_PFB_UNK_800					0x00100800



#define NV03_BOOT_0                                        0x00100000

#    define NV03_BOOT_0_RAM_AMOUNT                         0x00000003

#    define NV03_BOOT_0_RAM_AMOUNT_8MB                     0x00000000

#    define NV03_BOOT_0_RAM_AMOUNT_2MB                     0x00000001

#    define NV03_BOOT_0_RAM_AMOUNT_4MB                     0x00000002

#    define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM               0x00000003

#    define NV04_BOOT_0_RAM_AMOUNT_32MB                    0x00000000

#    define NV04_BOOT_0_RAM_AMOUNT_4MB                     0x00000001

#    define NV04_BOOT_0_RAM_AMOUNT_8MB                     0x00000002

#    define NV04_BOOT_0_RAM_AMOUNT_16MB                    0x00000003



#define NV04_FIFO_DATA                                     0x0010020c

#    define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK              0xfff00000

#    define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT             20

#define NV_PEXTDEV_BOOT_0					0x00101000

#define NV_PEXTDEV_BOOT_0_RAMCFG				0x0000003c

#	define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT		(8 << 12)

#define NV_PEXTDEV_BOOT_3					0x0010100c



#define NV_RAMIN                                           0x00700000
@@ -131,23 +176,6 @@ 
#define NV04_PTIMER_TIME_1                                 0x00009410

#define NV04_PTIMER_ALARM_0                                0x00009420



#define NV04_PFB_CFG0                                      0x00100200

#define NV04_PFB_CFG1                                      0x00100204

#define NV40_PFB_020C                                      0x0010020C

#define NV10_PFB_TILE(i)                                   (0x00100240 + (i*16))

#define NV10_PFB_TILE__SIZE                                8

#define NV10_PFB_TLIMIT(i)                                 (0x00100244 + (i*16))

#define NV10_PFB_TSIZE(i)                                  (0x00100248 + (i*16))

#define NV10_PFB_TSTATUS(i)                                (0x0010024C + (i*16))

#define NV10_PFB_CLOSE_PAGE2                               0x0010033C

#define NV40_PFB_TILE(i)                                   (0x00100600 + (i*16))

#define NV40_PFB_TILE__SIZE_0                              12

#define NV40_PFB_TILE__SIZE_1                              15

#define NV40_PFB_TLIMIT(i)                                 (0x00100604 + (i*16))

#define NV40_PFB_TSIZE(i)                                  (0x00100608 + (i*16))

#define NV40_PFB_TSTATUS(i)                                (0x0010060C + (i*16))

#define NV40_PFB_UNK_800					0x00100800



#define NV04_PGRAPH_DEBUG_0                                0x00400080

#define NV04_PGRAPH_DEBUG_1                                0x00400084

#define NV04_PGRAPH_DEBUG_2                                0x00400088

drivers/gpu/drm/nouveau/nv40_mc.c

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ nv40_mc_init(struct drm_device *dev) 
	case 0x46: /* G72 */

	case 0x4e:

	case 0x4c: /* C51_G7X */

		tmp = nv_rd32(dev, NV40_PFB_020C);

		tmp = nv_rd32(dev, NV04_PFB_FIFO_DATA);

		nv_wr32(dev, NV40_PMC_1700, tmp);

		nv_wr32(dev, NV40_PMC_1704, 0);

		nv_wr32(dev, NV40_PMC_1708, 0);