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Commit 3c5af8d1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc 

Pull sparc changes from David S Miller:
 "There is an attempt to fix a bad interaction between syscall tracing
  and force_successful_syscall() from Al Viro, but it needs to be redone
  as it introduced regressions and thus had to be reverted for now.

  Al is working on an updated version.

  But what we do have here are some significant bzero/memset
  improvements for Niagara-4.  An 8K page can be cleared in around 600
  cycles, because we essentially have a store that behaves like
  powerpc's dcbz that we can actually make real use of."

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  Revert strace hiccups fix.
  sparc64: Niagara-4 bzero/memset, plus use MRU stores in page copy.
  sparc64: Fix strace hiccups when force_successful_syscall() triggers.
  sparc64: Rearrange thread info to cheaply clear syscall noerror state.
parents e9eca4de 2863bc54

arch/sparc/include/asm/asi.h

+19 −0
Original line number Diff line number Diff line
@@ -270,9 +270,28 @@ 
#define ASI_BLK_INIT_QUAD_LDD_P	0xe2 /* (NG) init-store, twin load,

				      * primary, implicit

				      */

#define ASI_BLK_INIT_QUAD_LDD_S	0xe3 /* (NG) init-store, twin load,

				      * secondary, implicit

				      */

#define ASI_BLK_P		0xf0 /* Primary, blk ld/st		*/

#define ASI_BLK_S		0xf1 /* Secondary, blk ld/st		*/

#define ASI_ST_BLKINIT_MRU_P	0xf2 /* (NG4) init-store, twin load,

				      * Most-Recently-Used, primary,

				      * implicit

				      */

#define ASI_ST_BLKINIT_MRU_S	0xf2 /* (NG4) init-store, twin load,

				      * Most-Recently-Used, secondary,

				      * implicit

				      */

#define ASI_BLK_PL		0xf8 /* Primary, blk ld/st, little	*/

#define ASI_BLK_SL		0xf9 /* Secondary, blk ld/st, little	*/

#define ASI_ST_BLKINIT_MRU_PL	0xfa /* (NG4) init-store, twin load,

				      * Most-Recently-Used, primary,

				      * implicit, little-endian

				      */

#define ASI_ST_BLKINIT_MRU_SL	0xfb /* (NG4) init-store, twin load,

				      * Most-Recently-Used, secondary,

				      * implicit, little-endian

				      */



#endif /* _SPARC_ASI_H */

arch/sparc/kernel/head_64.S

+1 −1
Original line number Diff line number Diff line
@@ -576,7 +576,7 @@ niagara_tlb_fixup: 
niagara4_patch:

	call	niagara4_patch_copyops

	 nop

	call	niagara_patch_bzero

	call	niagara4_patch_bzero

	 nop

	call	niagara4_patch_pageops

	 nop

arch/sparc/lib/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ lib-$(CONFIG_SPARC64) += NG2memcpy.o NG2copy_from_user.o NG2copy_to_user.o 
lib-$(CONFIG_SPARC64) +=  NG2patch.o



lib-$(CONFIG_SPARC64) += NG4memcpy.o NG4copy_from_user.o NG4copy_to_user.o

lib-$(CONFIG_SPARC64) +=  NG4patch.o NG4copy_page.o

lib-$(CONFIG_SPARC64) +=  NG4patch.o NG4copy_page.o NG4clear_page.o NG4memset.o



lib-$(CONFIG_SPARC64) += GENmemcpy.o GENcopy_from_user.o GENcopy_to_user.o

lib-$(CONFIG_SPARC64) += GENpatch.o GENpage.o GENbzero.o

arch/sparc/lib/NG4clear_page.S

0 → 100644
+29 −0
Original line number Diff line number Diff line 
/* NG4copy_page.S: Niagara-4 optimized clear page.

 *

 * Copyright (C) 2012 (davem@davemloft.net)

 */



#include <asm/asi.h>

#include <asm/page.h>



	.text



	.register	%g3, #scratch



	.align		32

	.globl		NG4clear_page

	.globl		NG4clear_user_page

NG4clear_page:		/* %o0=dest */

NG4clear_user_page:	/* %o0=dest, %o1=vaddr */

	set		PAGE_SIZE, %g7

	mov		0x20, %g3

1:	stxa		%g0, [%o0 + %g0] ASI_ST_BLKINIT_MRU_P

	subcc		%g7, 0x40, %g7

	stxa		%g0, [%o0 + %g3] ASI_ST_BLKINIT_MRU_P

	bne,pt		%xcc, 1b

	 add		%o0, 0x40, %o0

	membar		#StoreLoad|#StoreStore

	retl

	 nop

	.size		NG4clear_page,.-NG4clear_page

	.size		NG4clear_user_page,.-NG4clear_user_page
 
 No newline at end of file

arch/sparc/lib/NG4copy_page.S

+8 −8
Original line number Diff line number Diff line
@@ -30,25 +30,25 @@ NG4copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */ 
	ldx		[%o1 + 0x10], %o4

	ldx		[%o1 + 0x18], %o5

	ldx		[%o1 + 0x20], %g1

	stxa		%o2, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%o2, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	ldx		[%o1 + 0x28], %g2

	stxa		%o3, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%o3, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	ldx		[%o1 + 0x30], %g3

	stxa		%o4, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%o4, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	ldx		[%o1 + 0x38], %o2

	add		%o1, 0x40, %o1

	stxa		%o5, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%o5, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	stxa		%g1, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%g1, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	stxa		%g2, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%g2, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	stxa		%g3, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%g3, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	stxa		%o2, [%o0] ASI_BLK_INIT_QUAD_LDD_P

	stxa		%o2, [%o0] ASI_ST_BLKINIT_MRU_P

	add		%o0, 0x08, %o0

	bne,pt		%icc, 1b

	 prefetch	[%o1 + 0x200], #n_reads_strong