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Commit 3ba5040a authored Jan 27, 2015 by James Hogan Committed by Ralf Baechle Mar 31, 2015

MIPS: cevt-r4k: Use CAUSEF_TI, CAUSEF_PCI constants



Use CAUSEF_TI and CAUSEF_PCI constants from asm/mipsregs.h rather than
the magic values (1 << 30) and (1 << 26).

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9124/


Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

parent 19971c0b

arch/mips/kernel/cevt-r4k.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -75,7 +75,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
		* above we now know that the reason we got here must be a timer
		* interrupt. Being the paranoiacs we are we check anyway.
		*/
		if (!r2 \|\| (read_c0_cause() & (1 << 30))) {
		if (!r2 \|\| (read_c0_cause() & CAUSEF_TI)) {
		/* Clear Count/Compare Interrupt */
		write_c0_compare(read_c0_compare());
		cd = &per_cpu(mips_clockevent_device, cpu);

arch/mips/oprofile/op_model_mipsxx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -246,7 +246,7 @@ static int mipsxx_perfcount_handler(void)
		unsigned int counter;
		int handled = IRQ_NONE;

		if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
		if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
		return handled;

		switch (counters) {