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Commit 3b40d07d authored by Younes Manton's avatar Younes Manton Committed by Ben Skeggs
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drm/nouveau: Calculate reserved VRAM for PRAMIN value before use. 



'drm/nouveau: rework vram init/fini ordering a little' changed
the order of instmem.init() and nouveau_mem_vram_init() which
resulted in using ramin_rsvd_vram before it was calculated and
failing to init any accel on pre-NV50 cards.

Since it's only used on <NV50 just calculate it where it's needed
and leave it as default 0 for NV50.

Signed-off-by: default avatarYounes Manton <younes.m@gmail.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 8fe198b2

drivers/gpu/drm/nouveau/nouveau_mem.c

+0 −28
Original line number Diff line number Diff line
@@ -423,34 +423,6 @@ nouveau_mem_vram_init(struct drm_device *dev) 
		return ret;

	}



	/* reserve space at end of VRAM for PRAMIN */

	if (dev_priv->card_type >= NV_50) {

		dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;

	} else

	if (dev_priv->card_type >= NV_40) {

		u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);

		u32 rsvd;



		/* estimate grctx size, the magics come from nv40_grctx.c */

		if      (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;

		else if (dev_priv->chipset  < 0x43) rsvd = 0x4f00 * vs;

		else if (nv44_graph_class(dev))	    rsvd = 0x4980 * vs;

		else				    rsvd = 0x4a40 * vs;

		rsvd += 16 * 1024;

		rsvd *= dev_priv->engine.fifo.channels;



		/* pciegart table */

		if (drm_pci_device_is_pcie(dev))

			rsvd += 512 * 1024;



		/* object storage */

		rsvd += 512 * 1024;



		dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);

	} else {

		dev_priv->ramin_rsvd_vram = 512 * 1024;

	}



	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));

	if (dev_priv->vram_sys_base) {

		NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",

drivers/gpu/drm/nouveau/nv04_instmem.c

+25 −0
Original line number Diff line number Diff line
@@ -28,6 +28,31 @@ int nv04_instmem_init(struct drm_device *dev) 
	/* RAMIN always available */

	dev_priv->ramin_available = true;



	/* Reserve space at end of VRAM for PRAMIN */

	if (dev_priv->card_type >= NV_40) {

		u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);

		u32 rsvd;



		/* estimate grctx size, the magics come from nv40_grctx.c */

		if      (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;

		else if (dev_priv->chipset  < 0x43) rsvd = 0x4f00 * vs;

		else if (nv44_graph_class(dev))	    rsvd = 0x4980 * vs;

		else				    rsvd = 0x4a40 * vs;

		rsvd += 16 * 1024;

		rsvd *= dev_priv->engine.fifo.channels;



		/* pciegart table */

		if (drm_pci_device_is_pcie(dev))

			rsvd += 512 * 1024;



		/* object storage */

		rsvd += 512 * 1024;



		dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);

	} else {

		dev_priv->ramin_rsvd_vram = 512 * 1024;

	}



	/* Setup shared RAMHT */

	ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096,

				      NVOBJ_FLAG_ZERO_ALLOC, &ramht);