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Commit 3b2cd4d0 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'sti-dt-for-v4.2-1' of... 

Merge tag 'sti-dt-for-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/dt

Pull "STi DT updates for v4.2, round 1." from Maxime Coquelin:

Highlights:
-----------
 - Add DT nodes for SSC on STiH407 family
 - Add DT nodes for SD/MMC on STiH407 & STiH418
 - Add DT node for LPC on STiH407
 - Add Sata DT nodes for STiH407
 - Fix PIO3 & PIO35 pins retiming on STiH407

* tag 'sti-dt-for-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
  ARM: DT: STi: STiH407: Add sata DT nodes.
  ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35
  ARM: STi: DT: STiH407: Add Device Tree node for the LPC
  mfd: dt-bindings: Provide human readable defines for LPC mode choosing
  ARM: STi: DT: STiH418: Add dt nodes for sdhci and emmc.
  ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.
  ARM: sti: Provide DT nodes for SBC SSC[0..2]
  ARM: sti: Provide DT nodes for SSC[0..4]
parents 905ea449 b3d37f92

arch/arm/boot/dts/stih407-family.dtsi

+180 −0
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 
 * publishhed by the Free Software Foundation.

 */

#include "stih407-pinctrl.dtsi"

#include <dt-bindings/mfd/st-lpc.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/reset-controller/stih407-resets.h>

/ {

	#address-cells = <1>;
@@ -336,5 +338,183 @@ 
				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;

			};

		};



		spi@9840000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9840000 0x110>;

			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";

			pinctrl-0 = <&pinctrl_spi0_default>;

			pinctrl-names = "default";

			#address-cells = <1>;

			#size-cells = <0>;



			status = "disabled";

		};



		spi@9841000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9841000 0x110>;

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";



			status = "disabled";

		};



		spi@9842000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9842000 0x110>;

			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";



			status = "disabled";

		};



		spi@9843000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9843000 0x110>;

			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";



			status = "disabled";

		};



		spi@9844000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9844000 0x110>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;

			clock-names = "ssc";



			status = "disabled";

		};



		/* SBC SSC */

		spi@9540000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9540000 0x110>;

			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_sysin>;

			clock-names = "ssc";



			status = "disabled";

		};



		spi@9541000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9541000 0x110>;

			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_sysin>;

			clock-names = "ssc";



			status = "disabled";

		};



		spi@9542000 {

			compatible = "st,comms-ssc4-spi";

			reg = <0x9542000 0x110>;

			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_sysin>;

			clock-names = "ssc";



			status = "disabled";

		};



		mmc0: sdhci@09060000 {

			compatible = "st,sdhci-stih407", "st,sdhci";

			status = "disabled";

			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;

			reg-names = "mmc", "top-mmc-delay";

			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;

			interrupt-names = "mmcirq";

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_mmc0>;

			clock-names = "mmc";

			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;

			bus-width = <8>;

			non-removable;

		};



		mmc1: sdhci@09080000 {

			compatible = "st,sdhci-stih407", "st,sdhci";

			status = "disabled";

			reg = <0x09080000 0x7ff>;

			reg-names = "mmc";

			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;

			interrupt-names = "mmcirq";

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_sd1>;

			clock-names = "mmc";

			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;

			resets = <&softreset STIH407_MMC1_SOFTRESET>;

			bus-width = <4>;

		};



		/* Watchdog and Real-Time Clock */

		lpc@8787000 {

			compatible = "st,stih407-lpc";

			reg = <0x8787000 0x1000>;

			interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;

			clocks = <&clk_s_d3_flexgen CLK_LPC_0>;

			timeout-sec = <120>;

			st,syscfg = <&syscfg_core>;

			st,lpc-mode = <ST_LPC_MODE_WDT>;

		};



		lpc@8788000 {

			compatible = "st,stih407-lpc";

			reg = <0x8788000 0x1000>;

			interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;

			clocks = <&clk_s_d3_flexgen CLK_LPC_1>;

			st,lpc-mode = <ST_LPC_MODE_RTC>;

		};



		sata0: sata@9b20000 {

			compatible = "st,ahci";

			reg = <0x9b20000 0x1000>;



			interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;

			interrupt-names = "hostc";



			phys = <&phy_port0 PHY_TYPE_SATA>;

			phy-names = "ahci_phy";



			resets = <&powerdown STIH407_SATA0_POWERDOWN>,

				 <&softreset STIH407_SATA0_SOFTRESET>,

				 <&softreset STIH407_SATA0_PWR_SOFTRESET>;

			reset-names = "pwr-dwn", "sw-rst", "pwr-rst";



			clock-names = "ahci_clk";

			clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;



			status = "disabled";

		};



		sata1: sata@9b28000 {

			compatible = "st,ahci";

			reg = <0x9b28000 0x1000>;



			interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;

			interrupt-names = "hostc";



			phys = <&phy_port1 PHY_TYPE_SATA>;

			phy-names = "ahci_phy";



			resets = <&powerdown STIH407_SATA1_POWERDOWN>,

				 <&softreset STIH407_SATA1_SOFTRESET>,

				 <&softreset STIH407_SATA1_PWR_SOFTRESET>;

			reset-names = "pwr-dwn",

				      "sw-rst",

				      "pwr-rst";



			clock-names = "ahci_clk";

			clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;



			status = "disabled";

		};

	};

};

arch/arm/boot/dts/stih407-pinctrl.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
				#interrupt-cells = <2>;

				reg = <0x5000 0x100>;

				st,bank-name = "PIO5";

				st,retime-pin-mask = <0x3f>;

			};



			rc {
@@ -519,6 +520,7 @@ 
				#interrupt-cells = <2>;

				reg = <0x5000 0x100>;

				st,bank-name = "PIO35";

				st,retime-pin-mask = <0x7f>;

			};



			i2c4 {

arch/arm/boot/dts/stih410-b2120.dts

+10 −0
Original line number Diff line number Diff line
@@ -26,4 +26,14 @@ 
	aliases {

		ttyAS0 = &sbc_serial0;

	};



	soc {



		mmc0: sdhci@09060000 {

			max-frequency = <200000000>;

			sd-uhs-sdr50;

			sd-uhs-sdr104;

			sd-uhs-ddr50;

		};

	};

};

arch/arm/boot/dts/stih418-b2199.dts

+12 −0
Original line number Diff line number Diff line
@@ -74,5 +74,17 @@ 
			st,i2c-min-scl-pulse-width-us = <0>;

			st,i2c-min-sda-pulse-width-us = <5>;

		};



		mmc1: sdhci@09080000 {

			status = "okay";

		};



		mmc0: sdhci@09060000 {

			status = "okay";

			max-frequency = <200000000>;

			sd-uhs-sdr50;

			sd-uhs-sdr104;

			sd-uhs-ddr50;

		};

	};

};

arch/arm/boot/dts/stihxxx-b2120.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -47,6 +47,14 @@ 
			status = "okay";

		};



		mmc0: sdhci@09060000 {

			status = "okay";

		};



		mmc1: sdhci@09080000 {

			status = "okay";

		};



		/* SSC11 to HDMI */

		hdmiddc: i2c@9541000 {

			status = "okay";