Merge branch 'for_tony_a_2.6.39rc' of git://git.pwsan.com/linux-2.6 into devel-fixes (3b1fb2ff) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/mach-omap2/clock44xx_data.c

+2 −7

Original line number	Original line	Diff line number	Diff line
	@@ -3116,14 +3116,9 @@ static struct omap_clk omap44xx_clks[] = {
	CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),		CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
	CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),		CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
	CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),		CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
	CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X),
	CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),		CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
	CLK("omapdss_dss", "fck", &dss_fck, CK_443X),		CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
	/*		CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
	* On OMAP4, DSS ick is a dummy clock; this is needed for compatibility
	* with OMAP2/3.
	*/
	CLK("omapdss_dss", "ick", &dummy_ck, CK_443X),
	CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),		CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
	CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),		CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
	CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),		CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),

arch/arm/mach-omap2/cm2xxx_3xxx.c

+17 −0

Original line number	Original line	Diff line number	Diff line
	@@ -247,6 +247,7 @@ struct omap3_cm_regs {
	u32 per_cm_clksel;		u32 per_cm_clksel;
	u32 emu_cm_clksel;		u32 emu_cm_clksel;
	u32 emu_cm_clkstctrl;		u32 emu_cm_clkstctrl;
			u32 pll_cm_autoidle;
	u32 pll_cm_autoidle2;		u32 pll_cm_autoidle2;
	u32 pll_cm_clksel4;		u32 pll_cm_clksel4;
	u32 pll_cm_clksel5;		u32 pll_cm_clksel5;
	@@ -319,6 +320,15 @@ void omap3_cm_save_context(void)
	omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
	cm_context.emu_cm_clkstctrl =		cm_context.emu_cm_clkstctrl =
	omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);		omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
			/*
			* As per erratum i671, ROM code does not respect the PER DPLL
			* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
			* In this case, even though this register has been saved in
			* scratchpad contents, we need to restore AUTO_PERIPH_DPLL
			* by ourselves. So, we need to save it anyway.
			*/
			cm_context.pll_cm_autoidle =
			omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
	cm_context.pll_cm_autoidle2 =		cm_context.pll_cm_autoidle2 =
	omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
	cm_context.pll_cm_clksel4 =		cm_context.pll_cm_clksel4 =
	@@ -441,6 +451,13 @@ void omap3_cm_restore_context(void)
	CM_CLKSEL1);		CM_CLKSEL1);
	omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,		omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
	OMAP2_CM_CLKSTCTRL);		OMAP2_CM_CLKSTCTRL);
			/*
			* As per erratum i671, ROM code does not respect the PER DPLL
			* programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
			* In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
			*/
			omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
			CM_AUTOIDLE);
	omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,		omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
	CM_AUTOIDLE2);		CM_AUTOIDLE2);
	omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,		omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,

arch/arm/mach-omap2/control.c

+7 −1

Original line number	Original line	Diff line number	Diff line
	@@ -316,8 +316,14 @@ void omap3_save_scratchpad_contents(void)
	omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);		omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
	prcm_block_contents.cm_clken_pll =		prcm_block_contents.cm_clken_pll =
	omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);		omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
			/*
			* As per erratum i671, ROM code does not respect the PER DPLL
			* programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
			* Then, in anycase, clear these bits to avoid extra latencies.
			*/
	prcm_block_contents.cm_autoidle_pll =		prcm_block_contents.cm_autoidle_pll =
	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);		omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
			~OMAP3430_AUTO_PERIPH_DPLL_MASK;
	prcm_block_contents.cm_clksel1_pll =		prcm_block_contents.cm_clksel1_pll =
	omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);		omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
	prcm_block_contents.cm_clksel2_pll =		prcm_block_contents.cm_clksel2_pll =

arch/arm/mach-omap2/omap_hwmod_2420_data.c

+5 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1639,6 +1639,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {

	static struct omap_hwmod omap2420_gpio1_hwmod = {		static struct omap_hwmod omap2420_gpio1_hwmod = {
	.name = "gpio1",		.name = "gpio1",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap242x_gpio1_irqs,		.mpu_irqs = omap242x_gpio1_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1669,6 +1670,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {

	static struct omap_hwmod omap2420_gpio2_hwmod = {		static struct omap_hwmod omap2420_gpio2_hwmod = {
	.name = "gpio2",		.name = "gpio2",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap242x_gpio2_irqs,		.mpu_irqs = omap242x_gpio2_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1699,6 +1701,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {

	static struct omap_hwmod omap2420_gpio3_hwmod = {		static struct omap_hwmod omap2420_gpio3_hwmod = {
	.name = "gpio3",		.name = "gpio3",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap242x_gpio3_irqs,		.mpu_irqs = omap242x_gpio3_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1729,6 +1732,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {

	static struct omap_hwmod omap2420_gpio4_hwmod = {		static struct omap_hwmod omap2420_gpio4_hwmod = {
	.name = "gpio4",		.name = "gpio4",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap242x_gpio4_irqs,		.mpu_irqs = omap242x_gpio4_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1782,7 +1786,7 @@ static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
	static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {		static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
	{		{
	.pa_start = 0x48056000,		.pa_start = 0x48056000,
	.pa_end = 0x4a0560ff,		.pa_end = 0x48056fff,
	.flags = ADDR_TYPE_RT		.flags = ADDR_TYPE_RT
	},		},
	};		};

arch/arm/mach-omap2/omap_hwmod_2430_data.c

+6 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1742,6 +1742,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {

	static struct omap_hwmod omap2430_gpio1_hwmod = {		static struct omap_hwmod omap2430_gpio1_hwmod = {
	.name = "gpio1",		.name = "gpio1",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap243x_gpio1_irqs,		.mpu_irqs = omap243x_gpio1_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1772,6 +1773,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {

	static struct omap_hwmod omap2430_gpio2_hwmod = {		static struct omap_hwmod omap2430_gpio2_hwmod = {
	.name = "gpio2",		.name = "gpio2",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap243x_gpio2_irqs,		.mpu_irqs = omap243x_gpio2_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1802,6 +1804,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {

	static struct omap_hwmod omap2430_gpio3_hwmod = {		static struct omap_hwmod omap2430_gpio3_hwmod = {
	.name = "gpio3",		.name = "gpio3",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap243x_gpio3_irqs,		.mpu_irqs = omap243x_gpio3_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1832,6 +1835,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {

	static struct omap_hwmod omap2430_gpio4_hwmod = {		static struct omap_hwmod omap2430_gpio4_hwmod = {
	.name = "gpio4",		.name = "gpio4",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap243x_gpio4_irqs,		.mpu_irqs = omap243x_gpio4_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
	.main_clk = "gpios_fck",		.main_clk = "gpios_fck",
	@@ -1862,6 +1866,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {

	static struct omap_hwmod omap2430_gpio5_hwmod = {		static struct omap_hwmod omap2430_gpio5_hwmod = {
	.name = "gpio5",		.name = "gpio5",
			.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
	.mpu_irqs = omap243x_gpio5_irqs,		.mpu_irqs = omap243x_gpio5_irqs,
	.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),		.mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
	.main_clk = "gpio5_fck",		.main_clk = "gpio5_fck",
	@@ -1915,7 +1920,7 @@ static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
	static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {		static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
	{		{
	.pa_start = 0x48056000,		.pa_start = 0x48056000,
	.pa_end = 0x4a0560ff,		.pa_end = 0x48056fff,
	.flags = ADDR_TYPE_RT		.flags = ADDR_TYPE_RT
	},		},
	};		};