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Commit 3a69ddd6 authored by Kenneth Graunke's avatar Kenneth Graunke Committed by Dave Airlie
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drm/i915: Set the Stencil Cache eviction policy to non-LRA mode. 

Clearing bit 5 of CACHE_MODE_0 is necessary to prevent GPU hangs in
OpenGL programs such as Google MapsGL, Google Earth, and gzdoom when
using separate stencil buffers.  Without it, the GPU tries to use the
LRA eviction policy, which isn't supported.  This was supposed to be off
by default, but seems to be on for many machines.

This cannot be done in gen6_init_clock_gating with most of the other
workaround bits; the render ring needs to exist.  Otherwise, the
register write gets dropped on the floor (one printk will show it
changed, but a second printk immediately following shows the value
reverts to the old one).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47535


Cc: stable@vger.kernel.org
Cc: Rob Castle <futuredub@gmail.com>
Cc: Eric Appleman <erappleman@gmail.com>
Cc: aaron667@gmx.net
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 700698e7

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -568,6 +568,7 @@ 
#define   CM0_MASK_SHIFT          16

#define   CM0_IZ_OPT_DISABLE      (1<<6)

#define   CM0_ZR_OPT_DISABLE      (1<<5)

#define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)

#define   CM0_DEPTH_EVICT_DISABLE (1<<4)

#define   CM0_COLOR_EVICT_DISABLE (1<<3)

#define   CM0_DEPTH_WRITE_DISABLE (1<<1)

drivers/gpu/drm/i915/intel_ringbuffer.c

+8 −0
Original line number Diff line number Diff line
@@ -401,6 +401,14 @@ static int init_render_ring(struct intel_ring_buffer *ring) 
	if (INTEL_INFO(dev)->gen >= 6) {

		I915_WRITE(INSTPM,

			   INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);



		/* From the Sandybridge PRM, volume 1 part 3, page 24:

		 * "If this bit is set, STCunit will have LRA as replacement

		 *  policy. [...] This bit must be reset.  LRA replacement

		 *  policy is not supported."

		 */

		I915_WRITE(CACHE_MODE_0,

			   CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);

	}



	return ret;