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Commit 3a1a344a authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by David Woodhouse
Browse files

mtd: nand: pxa3xx: Support command buffer #3 



Some newer controllers support a fourth command buffer. This additional
command buffer allows to set an arbitrary length count, using the
NDCB3.NDLENCNT field, to perform non-standard length operations
such as the ONFI parameter page read.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarDaniel Mack <zonque@gmail.com>
Signed-off-by: default avatarBrian Norris <computersforpeace@gmail.com>
Signed-off-by: default avatarDavid Woodhouse <David.Woodhouse@intel.com>
parent 5bb653e8

drivers/mtd/nand/pxa3xx_nand.c

+15 −0
Original line number Diff line number Diff line
@@ -197,6 +197,7 @@ struct pxa3xx_nand_info { 
	uint32_t		ndcb0;

	uint32_t		ndcb1;

	uint32_t		ndcb2;

	uint32_t		ndcb3;

};



static bool use_dma = 1;
@@ -493,9 +494,22 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) 
		nand_writel(info, NDSR, NDSR_WRCMDREQ);

		status &= ~NDSR_WRCMDREQ;

		info->state = STATE_CMD_HANDLE;



		/*

		 * Command buffer registers NDCB{0-2} (and optionally NDCB3)

		 * must be loaded by writing directly either 12 or 16

		 * bytes directly to NDCB0, four bytes at a time.

		 *

		 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored

		 * but each NDCBx register can be read.

		 */

		nand_writel(info, NDCB0, info->ndcb0);

		nand_writel(info, NDCB0, info->ndcb1);

		nand_writel(info, NDCB0, info->ndcb2);



		/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */

		if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)

			nand_writel(info, NDCB0, info->ndcb3);

	}



	/* clear NDSR to let the controller exit the IRQ */
@@ -554,6 +568,7 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command, 
	default:

		info->ndcb1 = 0;

		info->ndcb2 = 0;

		info->ndcb3 = 0;

		break;

	}