Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a062478 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Increase max fence pitch limit to 256KB on IVB+ 



BSpec contains several scattered notes which state that the maximum
fence stride was increased to 256KB on IVB.

Testing on real hardware agrees.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fe48d8de

drivers/gpu/drm/i915/i915_gem_tiling.c

+6 −3
Original line number Diff line number Diff line
@@ -217,9 +217,12 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 
		tile_width = 512;



	/* check maximum stride & object size */

	if (INTEL_INFO(dev)->gen >= 4) {

		/* i965 stores the end address of the gtt mapping in the fence

	/* i965+ stores the end address of the gtt mapping in the fence

	 * reg, so dont bother to check the size */

	if (INTEL_INFO(dev)->gen >= 7) {

		if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)

			return false;

	} else if (INTEL_INFO(dev)->gen >= 4) {

		if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)

			return false;

	} else {

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -430,6 +430,7 @@ 


#define FENCE_REG_SANDYBRIDGE_0		0x100000

#define   SANDYBRIDGE_FENCE_PITCH_SHIFT	32

#define   GEN7_FENCE_MAX_PITCH_VAL	0x0800



/* control register for cpu gtt access */

#define TILECTL				0x101000