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Commit 39e1d4c1 authored by Santosh Shilimkar's avatar Santosh Shilimkar
Browse files

ARM: OMAP4: SMP: Add mpu timer support for OMAP4430 



This patch adds SMP platform specific parts for local(mpu) timer support
for OMAP4430 platform. Each Cortex-a9 core has it's own local timer in the
MPU domain. These timers are not in wakeup domain.

Signed-off-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
parent 367cd31e

arch/arm/mach-omap2/timer-gp.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -38,6 +38,7 @@ 




#include <asm/mach/time.h>

#include <asm/mach/time.h>

#include <mach/dmtimer.h>

#include <mach/dmtimer.h>

#include <asm/localtimer.h>





/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */

/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */

#define MAX_GPTIMER_ID		12

#define MAX_GPTIMER_ID		12
@@ -229,6 +230,9 @@ static void __init omap2_gp_clocksource_init(void) 




static void __init omap2_gp_timer_init(void)

static void __init omap2_gp_timer_init(void)

{

{

#ifdef CONFIG_LOCAL_TIMERS

	twd_base = IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);

#endif

	omap_dm_timer_init();

	omap_dm_timer_init();





	omap2_gp_clockevent_init();

	omap2_gp_clockevent_init();

arch/arm/mach-omap2/timer-mpu.c

0 → 100644
+34 −0
Original line number Original line Diff line number Diff line 
/*

 * The MPU local timer source file. In OMAP4, both cortex-a9 cores have

 * own timer in it's MPU domain. These timers will be driving the

 * linux kernel SMP tick framework when active. These timers are not

 * part of the wake up domain.

 *

 * Copyright (C) 2009 Texas Instruments, Inc.

 *

 * Author:

 *      Santosh Shilimkar <santosh.shilimkar@ti.com>

 *

 * This file is based on arm realview smp platform file.

 * Copyright (C) 2002 ARM Ltd.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

#include <linux/init.h>

#include <linux/smp.h>

#include <linux/clockchips.h>

#include <asm/irq.h>

#include <asm/smp_twd.h>

#include <asm/localtimer.h>



/*

 * Setup the local clock events for a CPU.

 */

void __cpuinit local_timer_setup(struct clock_event_device *evt)

{

	evt->irq = INT_44XX_LOCALTIMER_IRQ;

	twd_timer_setup(evt);

}

arch/arm/plat-omap/include/mach/entry-macro.S

+28 −0
Original line number Original line Diff line number Diff line
@@ -136,6 +136,34 @@ 
		cmpne   \irqnr, \tmp

		cmpne   \irqnr, \tmp

		cmpcs   \irqnr, \irqnr

		cmpcs   \irqnr, \irqnr

		.endm

		.endm



		/* We assume that irqstat (the raw value of the IRQ acknowledge

		 * register) is preserved from the macro above.

		 * If there is an IPI, we immediately signal end of interrupt

		 * on the controller, since this requires the original irqstat

		 * value which we won't easily be able to recreate later.

		 */



		.macro test_for_ipi, irqnr, irqstat, base, tmp

		bic	\irqnr, \irqstat, #0x1c00

		cmp	\irqnr, #16

		it	cc

		strcc	\irqstat, [\base, #GIC_CPU_EOI]

		it	cs

		cmpcs	\irqnr, \irqnr

		.endm



		/* As above, this assumes that irqstat and base are preserved */



		.macro test_for_ltirq, irqnr, irqstat, base, tmp

		bic	\irqnr, \irqstat, #0x1c00

		mov 	\tmp, #0

		cmp	\irqnr, #29

		itt	eq

		moveq	\tmp, #1

		streq	\irqstat, [\base, #GIC_CPU_EOI]

		cmp	\tmp, #0

		.endm

#endif

#endif





		.macro	irq_prio_table

		.macro	irq_prio_table

arch/arm/plat-omap/include/mach/irqs.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -427,6 +427,8 @@ 








#define IRQ_GIC_START		32

#define IRQ_GIC_START		32

#define INT_44XX_LOCALTIMER_IRQ	29

#define INT_44XX_LOCALWDT_IRQ	30





#define INT_44XX_BENCH_MPU_EMUL	(3 + IRQ_GIC_START)

#define INT_44XX_BENCH_MPU_EMUL	(3 + IRQ_GIC_START)

#define INT_44XX_SSM_ABORT_IRQ	(6 + IRQ_GIC_START)

#define INT_44XX_SSM_ABORT_IRQ	(6 + IRQ_GIC_START)