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Commit 39c85666 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.9.100 into android-4.9 



Changes in 4.9.100
	ipvs: fix rtnl_lock lockups caused by start_sync_thread
	IB/device: Convert ib-comp-wq to be CPU-bound
	kcm: Call strp_stop before strp_done in kcm_attach
	crypto: af_alg - fix possible uninit-value in alg_bind()
	netlink: fix uninit-value in netlink_sendmsg
	net: fix rtnh_ok()
	net: initialize skb->peeked when cloning
	net: fix uninit-value in __hw_addr_add_ex()
	dccp: initialize ireq->ir_mark
	soreuseport: initialise timewait reuseport field
	perf: Remove superfluous allocation error check
	tcp: fix TCP_REPAIR_QUEUE bound checking
	bdi: Fix oops in wb_workfn()
	KVM: PPC: Book3S HV: Fix trap number return from __kvmppc_vcore_entry
	f2fs: fix a dead loop in f2fs_fiemap()
	arm64: Add work around for Arm Cortex-A55 Erratum 1024718
	gpioib: do not free unrequested descriptors
	gpio: fix aspeed_gpio unmask irq
	gpio: fix error path in lineevent_create
	rfkill: gpio: fix memory leak in probe error path
	libata: Apply NOLPM quirk for SanDisk SD7UB3Q*G1001 SSDs
	tracing: Fix regex_match_front() to not over compare the test string
	can: kvaser_usb: Increase correct stats counter in kvaser_usb_rx_can_msg()
	drm/vc4: Fix scaling of uni-planar formats
	drm/i915: Fix drm:intel_enable_lvds ERROR message in kernel log
	net: atm: Fix potential Spectre v1
	atm: zatm: Fix potential Spectre v1
	Revert "Bluetooth: btusb: Fix quirk for Atheros 1525/QCA6174"
	thermal: exynos: Reading temperature makes sense only when TMU is turned on
	thermal: exynos: Propagate error value from tmu_read()
	tracing/uprobe_event: Fix strncpy corner case
	perf/x86: Fix possible Spectre-v1 indexing for hw_perf_event cache_*
	perf/x86/cstate: Fix possible Spectre-v1 indexing for pkg_msr
	perf/x86/msr: Fix possible Spectre-v1 indexing in the MSR driver
	perf/core: Fix possible Spectre-v1 indexing for ->aux_pages[]
	perf/x86: Fix possible Spectre-v1 indexing for x86_pmu::event_map()
	Linux 4.9.100

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 74fa0af4 872e1aea

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

Makefile

+1 −1
Original line number Diff line number Diff line 
VERSION = 4

PATCHLEVEL = 9

SUBLEVEL = 99

SUBLEVEL = 100

EXTRAVERSION =

NAME = Roaring Lionus

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -429,6 +429,20 @@ config ARM64_ERRATUM_843419 


	  If unsure, say Y.



config ARM64_ERRATUM_1024718

	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"

	default y

	help

	  This option adds work around for Arm Cortex-A55 Erratum 1024718.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect

	  update of the hardware dirty bit when the DBM/AP bits are updated

	  without a break-before-make. The work around is to disable the usage

	  of hardware DBM locally on the affected cores. CPUs not affected by

	  erratum will continue to use the feature.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/assembler.h

+40 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/cputype.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>
@@ -462,4 +463,43 @@ alternative_endif 
	and	\phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)

	.endm



/*

 * Check the MIDR_EL1 of the current CPU for a given model and a range of

 * variant/revision. See asm/cputype.h for the macros used below.

 *

 *	model:		MIDR_CPU_MODEL of CPU

 *	rv_min:		Minimum of MIDR_CPU_VAR_REV()

 *	rv_max:		Maximum of MIDR_CPU_VAR_REV()

 *	res:		Result register.

 *	tmp1, tmp2, tmp3: Temporary registers

 *

 * Corrupts: res, tmp1, tmp2, tmp3

 * Returns:  0, if the CPU id doesn't match. Non-zero otherwise

 */

	.macro	cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3

	mrs		\res, midr_el1

	mov_q		\tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)

	mov_q		\tmp2, MIDR_CPU_MODEL_MASK

	and		\tmp3, \res, \tmp2	// Extract model

	and		\tmp1, \res, \tmp1	// rev & variant

	mov_q		\tmp2, \model

	cmp		\tmp3, \tmp2

	cset		\res, eq

	cbz		\res, .Ldone\@		// Model matches ?



	.if (\rv_min != 0)			// Skip min check if rv_min == 0

	mov_q		\tmp3, \rv_min

	cmp		\tmp1, \tmp3

	cset		\res, ge

	.endif					// \rv_min != 0

	/* Skip rv_max check if rv_min == rv_max && rv_min != 0 */

	.if ((\rv_min != \rv_max) || \rv_min == 0)

	mov_q		\tmp2, \rv_max

	cmp		\tmp1, \tmp2

	cset		\tmp2, le

	and		\res, \res, \tmp2

	.endif

.Ldone\@:

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/cputype.h

+5 −0
Original line number Diff line number Diff line
@@ -56,6 +56,9 @@ 
	(0xf			<< MIDR_ARCHITECTURE_SHIFT) | \

	((partnum)		<< MIDR_PARTNUM_SHIFT))



#define MIDR_CPU_VAR_REV(var, rev) \

	(((var) << MIDR_VARIANT_SHIFT) | (rev))



#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \

			     MIDR_ARCHITECTURE_MASK)
@@ -74,6 +77,7 @@ 


#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00

#define ARM_CPU_PART_CORTEX_A55		0xD05

#define ARM_CPU_PART_CORTEX_A57		0xD07

#define ARM_CPU_PART_CORTEX_A72		0xD08

#define ARM_CPU_PART_CORTEX_A53		0xD03
@@ -89,6 +93,7 @@ 
#define BRCM_CPU_PART_VULCAN		0x516



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)

#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)