Merge "msm: mdss: Fix race condition during mdp dump"

					60 = 60 frames per second (default)

- qcom,mdss-dsi-panel-clockrate:	A 64 bit value specifies the panel clock speed in Hz.

					0 = default value.

- qcom,mdss-mdp-kickoff-threshold:	This property can be used to define a region

					(in terms of scanlines) where the

hardware is allowed

					to trigger a data transfer from MDP to DSI.

					If this property is used, the region must be defined setting

					two values, the low and the high thresholds:

					<low_threshold high_threshold>

					Where following condition must be met:

					low_threshold < high_threshold

					These values will be used by the driver in such way that if

					the Driver receives a request to kickoff a transfer (MDP to DSI),

					the transfer will be triggered only if the following condition

					is satisfied:

					low_threshold < scanline < high_threshold

					If the condition is not met, then the driver will delay the

					transfer by the time defined in the following property:

					"qcom,mdss-mdp-kickoff-delay".

					So in order to use this property, the delay property must

					be defined as well and greater than 0.

- qcom,mdss-mdp-kickoff-delay:	This property defines the delay in microseconds that

					the driver will delay before triggering an MDP transfer if the

					thresholds defined by the following property are not met:

					"qcom,mdss-mdp-kickoff-threshold".

					So in order to use this property, the threshold property must

					be defined as well. Note that this delay cannot be zero

					and also should not be greater than

the fps window.

					i.e. For 60fps value should not exceed

16666 uS.

- qcom,mdss-mdp-transfer-time-us:	Specifies the dsi transfer time for command mode

					panels in microseconds. Driver uses this number to adjust

					the clock rate according to the expected transfer time.

		qcom,mdss-dsi-dma-trigger = <0>;

		qcom,mdss-dsi-panel-framerate = <60>;

		qcom,mdss-dsi-panel-clockrate = <424000000>;

		qcom,mdss-mdp-kickoff-threshold = <11 2430>;

		qcom,mdss-mdp-kickoff-delay = <1000>;

		qcom,mdss-mdp-transfer-time-us = <12500>;

		qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33

					22 27 1e 03 04 00];

#include "mdss_dsi.h"

#include "mdss_mdp.h"

#include "mdss_debug.h"

/*

 * mdss_check_te_status() - Check the status of panel for TE based ESD.

		ctl->ops.wait_pingpong(ctl, NULL);

	pr_debug("%s: DSI ctrl wait for ping pong done\n", __func__);

	MDSS_XLOG(mipi->mode);

	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON);

	ret = ctrl_pdata->check_status(ctrl_pdata);

	MDSS_QUIRK_NEED_SECURE_MAP,

	MDSS_QUIRK_SRC_SPLIT_ALWAYS,

	MDSS_QUIRK_HDR_SUPPORT_ENABLED,

	MDSS_QUIRK_MDP_CLK_SET_RATE,

	MDSS_QUIRK_MAX,

};

	u32 max_mdp_clk_rate;

	struct mdss_util_intf *mdss_util;

	struct mdss_panel_data *pdata;

	unsigned long mdp_clk_rate;

	struct platform_device *pdev;

	struct mdss_io_data mdss_io;

	u32 enable_gate;

	u32 enable_bw_release;

	u32 enable_rotator_bw_release;

	u32 enable_cdp;

	u32 serialize_wait4pp;

	u32 wait4autorefresh;

	u32 lines_before_active;

	u32 nmax_concurrent_ad_hw;

	struct workqueue_struct *ad_calc_wq;

	u32 ad_debugen;

	bool mem_retain;

	struct mdss_intr hist_intr;

	u32 splash_intf_sel;

	u32 splash_split_disp;

	struct mult_factor bus_throughput_factor;

};

extern struct mdss_data_type *mdss_res;

		commit32->commit_v1.input_layer_cnt;

	commit->commit_v1.left_roi = commit32->commit_v1.left_roi;

	commit->commit_v1.right_roi = commit32->commit_v1.right_roi;

	commit->commit_v1.bl_level = commit32->commit_v1.bl_level;

	memcpy(&commit->commit_v1.reserved, &commit32->commit_v1.reserved,

		count);

}

	compat_caddr_t		dest_scaler;

	uint32_t                dest_scaler_cnt;

	compat_caddr_t		frc_info;

	uint32_t		bl_level; /* BL level to be updated in commit */

	uint32_t		reserved[MDP_LAYER_COMMIT_V1_PAD];

};