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Commit 399cae74 authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: S3C64XX: Use new clock-clksrc.c code for clocks. 



Move the s3c6400-clock.c implementation over to use the new common
plat-samsung based clock-clksrc.c.

Note, this does not delete the clocks definitions that are now unused
in the regs-clock.h to reduce the quantity of change in this commit.

Based on original patches by Harald Welte.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent aa9ad6ad

arch/arm/plat-s3c64xx/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ config PLAT_S3C64XX 
	select ARM_VIC

	select NO_IOPORT

	select ARCH_REQUIRE_GPIOLIB

	select SAMSUNG_CLKSRC

	select S3C_GPIO_TRACK

	select S3C_GPIO_PULL_UPDOWN

	select S3C_GPIO_CFG_S3C24XX

arch/arm/plat-s3c64xx/s3c6400-clock.c

+39 −202
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 


#include <plat/regs-clock.h>

#include <plat/clock.h>

#include <plat/clock-clksrc.h>

#include <plat/cpu.h>

#include <plat/pll.h>
@@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = { 
#define clk_fout_mpll	clk_mpll

#define clk_fout_epll	clk_epll



struct clk_sources {

	unsigned int	nr_sources;

	struct clk	**sources;

};



struct clksrc_clk {

	struct clk		clk;

	unsigned int		mask;

	unsigned int		shift;



	struct clk_sources	*sources;



	unsigned int		divider_shift;

	void __iomem		*reg_divider;

};



static struct clk clk_fout_apll = {

	.name		= "fout_apll",

	.id		= -1,
@@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = { 
	[1] = &clk_fout_apll,

};



static struct clk_sources clk_src_apll = {

static struct clksrc_sources clk_src_apll = {

	.sources	= clk_src_apll_list,

	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),

};
@@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = { 
		.name		= "mout_apll",

		.id		= -1,

	},

	.shift		= S3C6400_CLKSRC_APLL_MOUT_SHIFT,

	.mask		= S3C6400_CLKSRC_APLL_MOUT,

	.reg_src	= { S3C_CLK_SRC, 0, 1 },

	.sources	= &clk_src_apll,

};
@@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = { 
	[1] = &clk_fout_epll,

};



static struct clk_sources clk_src_epll = {

static struct clksrc_sources clk_src_epll = {

	.sources	= clk_src_epll_list,

	.nr_sources	= ARRAY_SIZE(clk_src_epll_list),

};
@@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = { 
		.name		= "mout_epll",

		.id		= -1,

	},

	.shift		= S3C6400_CLKSRC_EPLL_MOUT_SHIFT,

	.mask		= S3C6400_CLKSRC_EPLL_MOUT,

	.reg_src	= { S3C_CLK_SRC, 2, 1 },

	.sources	= &clk_src_epll,

};
@@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = { 
	[1] = &clk_fout_mpll,

};



static struct clk_sources clk_src_mpll = {

static struct clksrc_sources clk_src_mpll = {

	.sources	= clk_src_mpll_list,

	.nr_sources	= ARRAY_SIZE(clk_src_mpll_list),

};
@@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = { 
		.name		= "mout_mpll",

		.id		= -1,

	},

	.shift		= S3C6400_CLKSRC_MPLL_MOUT_SHIFT,

	.mask		= S3C6400_CLKSRC_MPLL_MOUT,

	.reg_src	= { S3C_CLK_SRC, 1, 1 },

	.sources	= &clk_src_mpll,

};
@@ -214,7 +196,7 @@ static struct clk *clkset_spi_mmc_list[] = { 
	&clk_27m,

};



static struct clk_sources clkset_spi_mmc = {

static struct clksrc_sources clkset_spi_mmc = {

	.sources	= clkset_spi_mmc_list,

	.nr_sources	= ARRAY_SIZE(clkset_spi_mmc_list),

};
@@ -226,7 +208,7 @@ static struct clk *clkset_irda_list[] = { 
	&clk_27m,

};



static struct clk_sources clkset_irda = {

static struct clksrc_sources clkset_irda = {

	.sources	= clkset_irda_list,

	.nr_sources	= ARRAY_SIZE(clkset_irda_list),

};
@@ -238,7 +220,7 @@ static struct clk *clkset_uart_list[] = { 
	NULL

};



static struct clk_sources clkset_uart = {

static struct clksrc_sources clkset_uart = {

	.sources	= clkset_uart_list,

	.nr_sources	= ARRAY_SIZE(clkset_uart_list),

};
@@ -250,7 +232,7 @@ static struct clk *clkset_uhost_list[] = { 
	&clk_fin_epll,

};



static struct clk_sources clkset_uhost = {

static struct clksrc_sources clkset_uhost = {

	.sources	= clkset_uhost_list,

	.nr_sources	= ARRAY_SIZE(clkset_uhost_list),

};
@@ -265,94 +247,6 @@ static struct clk_sources clkset_uhost = { 
 * have a common parent divisor so are not included here.

 */



static inline struct clksrc_clk *to_clksrc(struct clk *clk)

{

	return container_of(clk, struct clksrc_clk, clk);

}



static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)

{

	struct clksrc_clk *sclk = to_clksrc(clk);

	unsigned long rate = clk_get_rate(clk->parent);

	u32 clkdiv = __raw_readl(sclk->reg_divider);



	clkdiv >>= sclk->divider_shift;

	clkdiv &= 0xf;

	clkdiv++;



	rate /= clkdiv;

	return rate;

}



static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)

{

	struct clksrc_clk *sclk = to_clksrc(clk);

	void __iomem *reg = sclk->reg_divider;

	unsigned int div;

	u32 val;



	rate = clk_round_rate(clk, rate);

	div = clk_get_rate(clk->parent) / rate;

	if (div > 16)

		return -EINVAL;



	val = __raw_readl(reg);

	val &= ~(0xf << sclk->divider_shift);

	val |= (div - 1) << sclk->divider_shift;

	__raw_writel(val, reg);



	return 0;

}



static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)

{

	struct clksrc_clk *sclk = to_clksrc(clk);

	struct clk_sources *srcs = sclk->sources;

	u32 clksrc = __raw_readl(S3C_CLK_SRC);

	int src_nr = -1;

	int ptr;



	for (ptr = 0; ptr < srcs->nr_sources; ptr++)

		if (srcs->sources[ptr] == parent) {

			src_nr = ptr;

			break;

		}



	if (src_nr >= 0) {

		clksrc &= ~sclk->mask;

		clksrc |= src_nr << sclk->shift;



		__raw_writel(clksrc, S3C_CLK_SRC);



		clk->parent = parent;

		return 0;

	}



	return -EINVAL;

}



static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,

					      unsigned long rate)

{

	unsigned long parent_rate = clk_get_rate(clk->parent);

	int div;



	if (rate > parent_rate)

		rate = parent_rate;

	else {

		div = parent_rate / rate;



		if (div == 0)

			div = 1;

		if (div > 16)

			div = 16;



		rate = parent_rate / div;

	}



	return rate;

}



/* clocks that feed other parts of the clock source tree */



static struct clk clk_iis_cd0 = {
@@ -378,7 +272,7 @@ static struct clk *clkset_audio0_list[] = { 
	[4] = &clk_pcm_cd,

};



static struct clk_sources clkset_audio0 = {

static struct clksrc_sources clkset_audio0 = {

	.sources	= clkset_audio0_list,

	.nr_sources	= ARRAY_SIZE(clkset_audio0_list),

};
@@ -391,7 +285,7 @@ static struct clk *clkset_audio1_list[] = { 
	[4] = &clk_pcm_cd,

};



static struct clk_sources clkset_audio1 = {

static struct clksrc_sources clkset_audio1 = {

	.sources	= clkset_audio1_list,

	.nr_sources	= ARRAY_SIZE(clkset_audio1_list),

};
@@ -400,7 +294,7 @@ static struct clk *clkset_camif_list[] = { 
	&clk_h2,

};



static struct clk_sources clkset_camif = {

static struct clksrc_sources clkset_camif = {

	.sources	= clkset_camif_list,

	.nr_sources	= ARRAY_SIZE(clkset_camif_list),

};
@@ -413,11 +307,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_MMC0,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_MMC0_SHIFT,

		.mask		= S3C6400_CLKSRC_MMC0_MASK,

		.reg_src	= { S3C_CLK_SRC, 18, 2 },

		.reg_div	= { S3C_CLK_DIV1, 0, 4 },

		.sources	= &clkset_spi_mmc,

		.divider_shift	= S3C6400_CLKDIV1_MMC0_SHIFT,

		.reg_divider	= S3C_CLK_DIV1,

	}, {

		.clk	= {

			.name		= "mmc_bus",
@@ -425,11 +317,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_MMC1,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_MMC1_SHIFT,

		.mask		= S3C6400_CLKSRC_MMC1_MASK,

		.reg_src	= { S3C_CLK_SRC, 20, 2 },

		.reg_div	= { S3C_CLK_DIV1, 4, 4 },

		.sources	= &clkset_spi_mmc,

		.divider_shift	= S3C6400_CLKDIV1_MMC1_SHIFT,

		.reg_divider	= S3C_CLK_DIV1,

	}, {

		.clk	= {

			.name		= "mmc_bus",
@@ -437,11 +327,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_MMC2,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_MMC2_SHIFT,

		.mask		= S3C6400_CLKSRC_MMC2_MASK,

		.reg_src	= { S3C_CLK_SRC, 22, 2 },

		.reg_div 	= { S3C_CLK_DIV1, 8, 4 },

		.sources	= &clkset_spi_mmc,

		.divider_shift	= S3C6400_CLKDIV1_MMC2_SHIFT,

		.reg_divider	= S3C_CLK_DIV1,

	}, {

		.clk	= {

			.name		= "usb-bus-host",
@@ -449,11 +337,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_UHOST,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_UHOST_SHIFT,

		.mask		= S3C6400_CLKSRC_UHOST_MASK,

		.reg_src 	= { S3C_CLK_SRC, 5, 2 },

		.reg_div	= { S3C_CLK_DIV1, 20, 4 },

		.sources	= &clkset_uhost,

		.divider_shift	= S3C6400_CLKDIV1_UHOST_SHIFT,

		.reg_divider	= S3C_CLK_DIV1,

	}, {

		.clk	= {

			.name		= "uclk1",
@@ -461,11 +347,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_UART,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_UART_SHIFT,

		.mask		= S3C6400_CLKSRC_UART_MASK,

		.reg_src	= { S3C_CLK_SRC, 13, 1 },

		.reg_div	= { S3C_CLK_DIV2, 16, 4 },

		.sources	= &clkset_uart,

		.divider_shift	= S3C6400_CLKDIV2_UART_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

/* Where does UCLK0 come from? */

		.clk	= {
@@ -474,11 +358,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_SPI0,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_SPI0_SHIFT,

		.mask		= S3C6400_CLKSRC_SPI0_MASK,

		.reg_src	= { S3C_CLK_SRC, 14, 2 },

		.reg_div	= { S3C_CLK_DIV2, 0, 4 },

		.sources	= &clkset_spi_mmc,

		.divider_shift	= S3C6400_CLKDIV2_SPI0_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

		.clk	= {

			.name		= "spi-bus",
@@ -486,11 +368,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_SPI1,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_SPI1_SHIFT,

		.mask		= S3C6400_CLKSRC_SPI1_MASK,

		.reg_src	= { S3C_CLK_SRC, 16, 2 },

		.reg_div	= { S3C_CLK_DIV2, 4, 4 },

		.sources	= &clkset_spi_mmc,

		.divider_shift	= S3C6400_CLKDIV2_SPI1_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

		.clk	= {

			.name		= "audio-bus",
@@ -498,11 +378,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_AUDIO0_SHIFT,

		.mask		= S3C6400_CLKSRC_AUDIO0_MASK,

		.reg_src	= { S3C_CLK_SRC, 7, 3 },

		.reg_div	= { S3C_CLK_DIV2, 8, 4 },

		.sources	= &clkset_audio0,

		.divider_shift	= S3C6400_CLKDIV2_AUDIO0_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

		.clk	= {

			.name		= "audio-bus",
@@ -510,11 +388,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_AUDIO1,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_AUDIO1_SHIFT,

		.mask		= S3C6400_CLKSRC_AUDIO1_MASK,

		.reg_src	= { S3C_CLK_SRC, 10, 3 },

		.reg_div	= { S3C_CLK_DIV2, 12, 4 },

		.sources	= &clkset_audio1,

		.divider_shift	= S3C6400_CLKDIV2_AUDIO1_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

		.clk	= {

			.name		= "irda-bus",
@@ -522,11 +398,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_IRDA,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= S3C6400_CLKSRC_IRDA_SHIFT,

		.mask		= S3C6400_CLKSRC_IRDA_MASK,

		.reg_src	= { S3C_CLK_SRC, 24, 2 },

		.reg_div	= { S3C_CLK_DIV2, 20, 4 },

		.sources	= &clkset_irda,

		.divider_shift	= S3C6400_CLKDIV2_IRDA_SHIFT,

		.reg_divider	= S3C_CLK_DIV2,

	}, {

		.clk	= {

			.name		= "camera",
@@ -534,11 +408,9 @@ static struct clksrc_clk clksrcs[] = { 
			.ctrlbit        = S3C_CLKCON_SCLK_CAM,

			.enable		= s3c64xx_sclk_ctrl,

		},

		.shift		= 0,

		.mask		= 0,

		.reg_div	= { S3C_CLK_DIV0, 20, 4 },

		.reg_src	= { NULL, 0, 0 },

		.sources	= &clkset_camif,

		.divider_shift	= S3C6400_CLKDIV0_CAM_SHIFT,

		.reg_divider	= S3C_CLK_DIV0,

	},

};
@@ -550,27 +422,6 @@ static struct clksrc_clk *init_parents[] = { 
	&clk_mout_mpll,

};



static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)

{

	struct clk_sources *srcs = clk->sources;

	u32 clksrc = __raw_readl(S3C_CLK_SRC);



	clksrc &= clk->mask;

	clksrc >>= clk->shift;



	if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {

		printk(KERN_ERR "%s: bad source %d\n",

		       clk->clk.name, clksrc);

		return;

	}



	clk->clk.parent = srcs->sources[clksrc];



	printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",

	       clk->clk.name, clk->clk.parent->name, clksrc,

	       clk_get_rate(&clk->clk));

}



#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)



void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -629,10 +480,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) 
	clk_f.rate = fclk;



	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)

		s3c6400_set_clksrc(init_parents[ptr]);

		s3c_set_clksrc(init_parents[ptr]);



	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)

		s3c6400_set_clksrc(&clksrcs[ptr]);

		s3c_set_clksrc(&clksrcs[ptr]);

}



static struct clk *clks[] __initdata = {
@@ -675,19 +526,5 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) 
		}

	}



	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) {

		clkp = &clksrcs[ptr].clk;



		/* all clksrc clocks have these */

		clkp->get_rate = s3c64xx_getrate_clksrc;

		clkp->set_rate = s3c64xx_setrate_clksrc;

		clkp->set_parent = s3c64xx_setparent_clksrc;

		clkp->round_rate = s3c64xx_roundrate_clksrc;



		ret = s3c24xx_register_clock(clkp);

		if (ret < 0) {

			printk(KERN_ERR "Failed to register clock %s (%d)\n",

			       clkp->name, ret);

		}

	}

	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));

}