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Commit 39409aa4 authored by Thierry Reding's avatar Thierry Reding Committed by Peter De Schrijver
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clk: tegra: Initialize DSI low-power clocks 



The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 5ab5d404

drivers/clk/tegra/clk-tegra114.c

+2 −0
Original line number Diff line number Diff line
@@ -1299,6 +1299,8 @@ static struct tegra_clk_init_table init_table[] __initdata = { 
	{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},

	{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},

	{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},

	{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},

	{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},



	/* This MUST be the last entry. */

	{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},