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Commit 393ee3d1 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "UPSTREAM: Merge remote-tracking branch 'quic/dev/msm-4.9-camx' into msm-4.9_UPSTREAM_0905"

parents 6d6d60c0 435e9447

Documentation/devicetree/bindings/media/video/msm-cam-fd.txt

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+149 −0
Original line number Diff line number Diff line 
* Qualcomm Technologies, Inc. MSM Camera FD



The MSM camera Face Detection device provides dependency definitions

for enabling Camera FD HW. MSM camera FD is implemented in multiple

device nodes. The root FD device node has properties defined to hint

the driver about the FD HW nodes available during the probe sequence.

Each node has multiple properties defined for interrupts, clocks and

regulators.



=======================

Required Node Structure

=======================

FD root interface node takes care of the handling Face Detection high level

driver handling and controls underlying FD hardware present.



- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,cam-fd".



- compat-hw-name

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,fd".



- num-fd

  Usage: required

  Value type: <u32>

  Definition: Number of supported FD HW blocks.



Example:

	qcom,cam-fd {

		compatible = "qcom,cam-fd";

		compat-hw-name = "qcom,fd";

		num-fd = <1>;

	};



=======================

Required Node Structure

=======================

FD Node provides interface for Face Detection hardware driver

about the device register map, interrupt map, clocks, regulators.



- cell-index

  Usage: required

  Value type: <u32>

  Definition: Node instance number.



- compatible

  Usage: required

  Value type: <string>

  Definition: Should be "qcom,fd41".



- reg-names

  Usage: optional

  Value type: <string>

  Definition: Name of the register resources.



- reg

  Usage: optional

  Value type: <u32>

  Definition: Register values.



- reg-cam-base

  Usage: optional

  Value type: <u32>

  Definition: Offset of the register space compared to

              to Camera base register space.



- interrupt-names

  Usage: optional

  Value type: <string>

  Definition: Name of the interrupt.



- interrupts

  Usage: optional

  Value type: <u32>

  Definition: Interrupt line associated with FD HW.



- regulator-names

  Usage: required

  Value type: <string>

  Definition: Name of the regulator resources for FD HW.



- camss-vdd-supply

  Usage: required

  Value type: <phandle>

  Definition: Regulator reference corresponding to the names listed

              in "regulator-names".



- clock-names

  Usage: required

  Value type: <string>

  Definition: List of clock names required for FD HW.



- clocks

  Usage: required

  Value type: <phandle>

  Definition: List of clocks required for FD HW.



- clock-rates

  Usage: required

  Value type: <u32>

  Definition: List of clocks rates.



- src-clock-name

  Usage: required

  Value type: <string>

  Definition: Source clock name.



- clock-cntl-level

  Usage: required

  Value type: <string>

  Definition: List of strings corresponds clock-rates levels.

  Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo.



Examples:

	cam_fd: qcom,fd@ac5a000 {

		cell-index = <0>;

		compatible = "qcom,fd41";

		reg-names = "fd_core", "fd_wrapper";

		reg = <0xac5a000 0x1000>,

			<0xac5b000 0x400>;

		reg-cam-base = <0x5a000 0x5b000>;

		interrupt-names = "fd";

		interrupts = <0 462 0>;

		regulator-names = "camss-vdd";

		camss-vdd-supply = <&titan_top_gdsc>;

		clock-names = "gcc_ahb_clk",

			"gcc_axi_clk",

			"soc_ahb_clk",

			"cpas_ahb_clk",

			"camnoc_axi_clk",

			"fd_core_clk_src",

			"fd_core_clk",

			"fd_core_uar_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,

			<&clock_gcc GCC_CAMERA_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_FD_CORE_CLK_SRC>,

			<&clock_camcc CAM_CC_FD_CORE_CLK>,

			<&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;

		src-clock-name = "fd_core_clk_src";

		clock-cntl-level = "svs";

		clock-rates = <0 0 0 0 0 400000000 0 0>;

	};

Documentation/devicetree/bindings/media/video/msm-cam-icp.txt

+30 −7
Original line number Diff line number Diff line
@@ -105,6 +105,11 @@ and name of firmware image. 
  Value type: <string>

  Definition: List of clock names required for CDM HW.



- src-clock-name

  Usage: required

  Value type: <string>

  Definition: Source clock name.



- clocks

  Usage: required

  Value type: <phandle>
@@ -114,7 +119,7 @@ and name of firmware image. 
  Usage: required

  Value type: <string>

  Definition: List of strings corresponds clock-rates levels.

  Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo.

  Supported strings: lowsvs, svs, svs_l1, nominal, turbo.



- clock-rates

  Usage: required
@@ -176,14 +181,20 @@ qcom,ipe0 { 
		"ipe_0_axi_clk",

		"ipe_0_clk",

		"ipe_0_clk_src";

	src-clock-name = "ipe_0_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 240000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 538000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};



qcom,ipe1 {
@@ -196,14 +207,20 @@ qcom,ipe1 { 
		"ipe_1_axi_clk",

		"ipe_1_clk",

		"ipe_1_clk_src";

	src-clock-name = "ipe_1_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 240000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 538000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};



bps: qcom,bps {
@@ -216,13 +233,19 @@ bps: qcom,bps { 
		"bps_axi_clk",

		"bps_clk",

		"bps_clk_src";

	src-clock-name = "bps_clk_src";

	clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

			<&clock_camcc CAM_CC_BPS_AREG_CLK>,

			<&clock_camcc CAM_CC_BPS_AXI_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 200000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 600000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};

arch/arm64/boot/dts/qcom/sdm845-camera.dtsi

+79 −6
Original line number Diff line number Diff line
@@ -338,6 +338,22 @@ 
				};

			};

		};



		msm_cam_smmu_fd {

			compatible = "qcom,msm-cam-smmu-cb";

			iommus = <&apps_smmu 0x1070 0x0>;

			label = "fd";

			fd_iova_mem_map: iova-mem-map {

				iova-mem-region-io {

					/* IO region is approximately 3.4 GB */

					iova-region-name = "io";

					iova-region-start = <0x7400000>;

					iova-region-len = <0xd8c00000>;

					iova-region-id = <0x3>;

					status = "ok";

				};

			};

		};

	};



	qcom,cam-cpas@ac40000 {
@@ -840,14 +856,20 @@ 
			"ipe_0_axi_clk",

			"ipe_0_clk",

			"ipe_0_clk_src";

		src-clock-name = "ipe_0_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 240000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 538000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};
@@ -861,14 +883,20 @@ 
			"ipe_1_axi_clk",

			"ipe_1_clk",

			"ipe_1_clk_src";

		src-clock-name = "ipe_1_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 240000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 538000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};
@@ -882,14 +910,20 @@ 
			"bps_axi_clk",

			"bps_clk",

			"bps_clk_src";

		src-clock-name = "bps_clk_src";

		clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

				<&clock_camcc CAM_CC_BPS_AREG_CLK>,

				<&clock_camcc CAM_CC_BPS_AXI_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 200000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 600000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};
@@ -964,4 +998,43 @@ 
		status = "ok";

	};



	qcom,cam-fd {

		compatible = "qcom,cam-fd";

		compat-hw-name = "qcom,fd";

		num-fd = <1>;

		status = "ok";

	};



	cam_fd: qcom,fd@ac5a000 {

		cell-index = <0>;

		compatible = "qcom,fd41";

		reg-names = "fd_core", "fd_wrapper";

		reg = <0xac5a000 0x1000>,

			<0xac5b000 0x400>;

		reg-cam-base = <0x5a000 0x5b000>;

		interrupt-names = "fd";

		interrupts = <0 462 0>;

		regulator-names = "camss-vdd";

		camss-vdd-supply = <&titan_top_gdsc>;

		clock-names = "gcc_ahb_clk",

			"gcc_axi_clk",

			"soc_ahb_clk",

			"cpas_ahb_clk",

			"camnoc_axi_clk",

			"fd_core_clk_src",

			"fd_core_clk",

			"fd_core_uar_clk";

		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,

			<&clock_gcc GCC_CAMERA_AXI_CLK>,

			<&clock_camcc CAM_CC_SOC_AHB_CLK>,

			<&clock_camcc CAM_CC_CPAS_AHB_CLK>,

			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,

			<&clock_camcc CAM_CC_FD_CORE_CLK_SRC>,

			<&clock_camcc CAM_CC_FD_CORE_CLK>,

			<&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;

		src-clock-name = "fd_core_clk_src";

		clock-cntl-level = "svs";

		clock-rates = <0 0 0 0 0 400000000 0 0>;

		status = "ok";

	};

};

drivers/media/platform/msm/camera/Makefile

+1 −0
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@@ -9,3 +9,4 @@ obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp/ 
obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd/

drivers/media/platform/msm/camera/cam_fd/Makefile

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+14 −0
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ccflags-y += -Idrivers/media/platform/msm/camera/cam_utils

ccflags-y += -Idrivers/media/platform/msm/camera/cam_req_mgr

ccflags-y += -Idrivers/media/platform/msm/camera/cam_core

ccflags-y += -Idrivers/media/platform/msm/camera/cam_sync

ccflags-y += -Idrivers/media/platform/msm/camera/cam_smmu

ccflags-y += -Idrivers/media/platform/msm/camera/cam_cdm

ccflags-y += -Idrivers/media/platform/msm/camera/cam_fd

ccflags-y += -Idrivers/media/platform/msm/camera/cam_fd/fd_hw_mgr

ccflags-y += -Idrivers/media/platform/msm/camera/cam_fd/fd_hw_mgr/fd_hw

ccflags-y += -Idrivers/media/platform/msm/camera

ccflags-y += -Idrivers/media/platform/msm/camera/cam_cpas/include



obj-$(CONFIG_SPECTRA_CAMERA) += fd_hw_mgr/

obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_dev.o cam_fd_context.o