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Commit 38e5e92f authored by Joerg Roedel's avatar Joerg Roedel Committed by Avi Kivity
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KVM: SVM: Implement Flush-By-Asid feature



This patch adds the new flush-by-asid of upcoming AMD
processors to the KVM-AMD module.

Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
parent f40f6a45
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+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ struct __attribute__ ((__packed__)) vmcb_control_area {

#define TLB_CONTROL_DO_NOTHING 0
#define TLB_CONTROL_FLUSH_ALL_ASID 1
#define TLB_CONTROL_FLUSH_ASID 3
#define TLB_CONTROL_FLUSH_ASID_LOCAL 7

#define V_TPR_MASK 0x0f

+8 −2
Original line number Diff line number Diff line
@@ -3158,7 +3158,6 @@ static void pre_svm_run(struct vcpu_svm *svm)

	struct svm_cpu_data *sd = per_cpu(svm_data, cpu);

	svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
	/* FIXME: handle wraparound of asid_generation */
	if (svm->asid_generation != sd->asid_generation)
		new_asid(svm, sd);
@@ -3303,7 +3302,12 @@ static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)

static void svm_flush_tlb(struct kvm_vcpu *vcpu)
{
	to_svm(vcpu)->asid_generation--;
	struct vcpu_svm *svm = to_svm(vcpu);

	if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
		svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
	else
		svm->asid_generation--;
}

static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
@@ -3529,6 +3533,8 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)

	svm->next_rip = 0;

	svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;

	/* if exit due to PF check for async PF */
	if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
		svm->apf_reason = kvm_read_and_reset_pf_reason();