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Commit 3863c74b authored by Thara Gopinath's avatar Thara Gopinath Committed by paul
Browse files

OMAP3: PM: Fix for MPU power domain MEM BANK position



MPU power domain bank 0 bits are displayed in position of bank 1
in PWRSTS and PREPWRSTS registers. So read them from correct
position

Signed-off-by: default avatarThara Gopinath <thara@ti.com>
Signed-off-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 18862cbe
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+6 −0
Original line number Diff line number Diff line
@@ -983,6 +983,9 @@ int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
	if (pwrdm->banks < (bank + 1))
		return -EEXIST;

	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
		bank = 1;

	/*
	 * The register bit names below may not correspond to the
	 * actual names of the bits in each powerdomain's register,
@@ -1030,6 +1033,9 @@ int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
	if (pwrdm->banks < (bank + 1))
		return -EEXIST;

	if (pwrdm->flags & PWRDM_HAS_MPU_QUIRK)
		bank = 1;

	/*
	 * The register bit names below may not correspond to the
	 * actual names of the bits in each powerdomain's register,
+1 −0
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ static struct powerdomain mpu_34xx_pwrdm = {
	.wkdep_srcs	  = mpu_34xx_wkdeps,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
+4 −1
Original line number Diff line number Diff line
@@ -42,7 +42,10 @@

/* Powerdomain flags */
#define PWRDM_HAS_HDWR_SAR	(1 << 0) /* hardware save-and-restore support */

#define PWRDM_HAS_MPU_QUIRK	(1 << 1) /* MPU pwr domain has MEM bank 0 bits
					  * in MEM bank 1 position. This is
					  * true for OMAP3430
					  */

/*
 * Number of memory banks that are power-controllable.	On OMAP3430, the