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Commit 38506ece authored by Larry Finger's avatar Larry Finger Committed by John W. Linville
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rtlwifi: rtl_pci: Start modification for new drivers



Future patches will move the drivers for RTL8192EE and RTL8821AE
from staging to the regular wireless tree. Here, the necessary features
are added to the PCI driver. Other files are touched due to changes
in the various data structs.

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent fd09ff95
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+1 −14
Original line number Original line Diff line number Diff line
@@ -129,19 +129,6 @@ void rtl_fw_cb(const struct firmware *firmware, void *context)
	memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
	memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
	rtlpriv->rtlhal.fwsize = firmware->size;
	rtlpriv->rtlhal.fwsize = firmware->size;
	release_firmware(firmware);
	release_firmware(firmware);

	err = ieee80211_register_hw(hw);
	if (err) {
		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
			 "Can't register mac80211 hw\n");
		return;
	} else {
		rtlpriv->mac80211.mac80211_registered = 1;
	}
	set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);

	/*init rfkill */
	rtl_init_rfkill(hw);
}
}
EXPORT_SYMBOL(rtl_fw_cb);
EXPORT_SYMBOL(rtl_fw_cb);


@@ -1392,7 +1379,7 @@ static void rtl_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_priv *rtlpriv = rtl_priv(hw);


	if (rtlpriv->intf_ops->flush)
	if (rtlpriv->intf_ops->flush)
		rtlpriv->intf_ops->flush(hw, drop);
		rtlpriv->intf_ops->flush(hw, queues, drop);
}
}


const struct ieee80211_ops rtl_ops = {
const struct ieee80211_ops rtl_ops = {
+3 −7
Original line number Original line Diff line number Diff line
@@ -2,20 +2,16 @@
 *
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 *
 * Tmis program is free software; you can redistribute it and/or modify it
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 * published by the Free Software Foundation.
 *
 *
 * Tmis program is distributed in the hope that it will be useful, but WITHOUT
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 * more details.
 *
 *
 * You should have received a copy of the GNU General Public License along with
 * The full GNU General Public License is included in this distribution in the
 * tmis program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * Tme full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 * file called LICENSE.
 *
 *
 * Contact Information:
 * Contact Information:
+548 −301

File changed.

Preview size limit exceeded, changes collapsed.

+45 −11
Original line number Original line Diff line number Diff line
@@ -39,10 +39,11 @@
#define RTL_PCI_RX_CMD_QUEUE			1
#define RTL_PCI_RX_CMD_QUEUE			1
#define RTL_PCI_MAX_RX_QUEUE			2
#define RTL_PCI_MAX_RX_QUEUE			2


#define RTL_PCI_MAX_RX_COUNT			64
#define RTL_PCI_MAX_RX_COUNT			512/*64*/
#define RTL_PCI_MAX_TX_QUEUE_COUNT		9
#define RTL_PCI_MAX_TX_QUEUE_COUNT		9


#define RT_TXDESC_NUM				128
#define RT_TXDESC_NUM				128
#define TX_DESC_NUM_92E				512
#define RT_TXDESC_NUM_BE_QUEUE			256
#define RT_TXDESC_NUM_BE_QUEUE			256


#define BK_QUEUE				0
#define BK_QUEUE				0
@@ -62,6 +63,12 @@
	.subdevice = PCI_ANY_ID,\
	.subdevice = PCI_ANY_ID,\
	.driver_data = (kernel_ulong_t)&(cfg)
	.driver_data = (kernel_ulong_t)&(cfg)


#define INTEL_VENDOR_ID				0x8086
#define SIS_VENDOR_ID				0x1039
#define ATI_VENDOR_ID				0x1002
#define ATI_DEVICE_ID				0x7914
#define AMD_VENDOR_ID				0x1022

#define PCI_MAX_BRIDGE_NUMBER			255
#define PCI_MAX_BRIDGE_NUMBER			255
#define PCI_MAX_DEVICES				32
#define PCI_MAX_DEVICES				32
#define PCI_MAX_FUNCTION			8
#define PCI_MAX_FUNCTION			8
@@ -69,6 +76,11 @@
#define PCI_CONF_ADDRESS	0x0CF8	/*PCI Configuration Space Address */
#define PCI_CONF_ADDRESS	0x0CF8	/*PCI Configuration Space Address */
#define PCI_CONF_DATA		0x0CFC	/*PCI Configuration Space Data */
#define PCI_CONF_DATA		0x0CFC	/*PCI Configuration Space Data */


#define PCI_CLASS_BRIDGE_DEV		0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI	0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS	0x10
#define PCI_CAP_ID_EXP			0x10

#define U1DONTCARE			0xFF
#define U1DONTCARE			0xFF
#define U2DONTCARE			0xFFFF
#define U2DONTCARE			0xFFFF
#define U4DONTCARE			0xFFFFFFFF
#define U4DONTCARE			0xFFFFFFFF
@@ -87,6 +99,7 @@
#define RTL_PCI_700F_DID	0x700F
#define RTL_PCI_700F_DID	0x700F
#define RTL_PCI_701F_DID	0x701F
#define RTL_PCI_701F_DID	0x701F
#define RTL_PCI_DLINK_DID	0x3304
#define RTL_PCI_DLINK_DID	0x3304
#define RTL_PCI_8723AE_DID	0x8723	/*8723e */
#define RTL_PCI_8192CET_DID	0x8191	/*8192ce */
#define RTL_PCI_8192CET_DID	0x8191	/*8192ce */
#define RTL_PCI_8192CE_DID	0x8178	/*8192ce */
#define RTL_PCI_8192CE_DID	0x8178	/*8192ce */
#define RTL_PCI_8191CE_DID	0x8177	/*8192ce */
#define RTL_PCI_8191CE_DID	0x8177	/*8192ce */
@@ -95,6 +108,10 @@
#define RTL_PCI_8192DE_DID	0x8193	/*8192de */
#define RTL_PCI_8192DE_DID	0x8193	/*8192de */
#define RTL_PCI_8192DE_DID2	0x002B	/*92DE*/
#define RTL_PCI_8192DE_DID2	0x002B	/*92DE*/
#define RTL_PCI_8188EE_DID	0x8179  /*8188ee*/
#define RTL_PCI_8188EE_DID	0x8179  /*8188ee*/
#define RTL_PCI_8723BE_DID	0xB723  /*8723be*/
#define RTL_PCI_8192EE_DID	0x818B	/*8192ee*/
#define RTL_PCI_8821AE_DID	0x8821	/*8821ae*/
#define RTL_PCI_8812AE_DID	0x8812	/*8812ae*/


/*8192 support 16 pages of IO registers*/
/*8192 support 16 pages of IO registers*/
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI		0x1000
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI		0x1000
@@ -125,24 +142,34 @@ struct rtl_pci_capabilities_header {
	u8 next;
	u8 next;
};
};


struct rtl_rx_desc {
/* In new TRX flow, Buffer_desc is new concept
	u32 dword[8];
 * But TX wifi info == TX descriptor in old flow
 * RX wifi info == RX descriptor in old flow
 */
struct rtl_tx_buffer_desc {
#if (RTL8192EE_SEG_NUM == 2)
	u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
#elif (RTL8192EE_SEG_NUM == 1)
	u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
#elif (RTL8192EE_SEG_NUM == 0)
	u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
#endif
} __packed;
} __packed;


struct rtl_tx_desc {
struct rtl_tx_desc {
	u32 dword[16];
	u32 dword[16];
} __packed;
} __packed;


struct rtl_tx_cmd_desc {
struct rtl_rx_buffer_desc { /*rx buffer desc*/
	u32 dword[16];
	u32 dword[2];
} __packed;
} __packed;


/* In new TRX flow, Buffer_desc is new concept
struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
 * But TX wifi info == TX descriptor in old flow
	u32 dword[8];
 * RX wifi info == RX descriptor in old flow
} __packed;
 */

struct rtl_tx_buffer_desc {
struct rtl_tx_cmd_desc {
	u32 dword[8]; /*seg = 4*/
	u32 dword[16];
} __packed;
} __packed;


struct rtl8192_tx_ring {
struct rtl8192_tx_ring {
@@ -153,6 +180,10 @@ struct rtl8192_tx_ring {
	struct sk_buff_head queue;
	struct sk_buff_head queue;
	/*add for new trx flow*/
	/*add for new trx flow*/
	struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
	struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
	dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
	u16 avl_desc; /* available_desc_to_write */
	u16 cur_tx_wp; /* current_tx_write_point */
	u16 cur_tx_rp; /* current_tx_read_point */
};
};


struct rtl8192_rx_ring {
struct rtl8192_rx_ring {
@@ -160,6 +191,9 @@ struct rtl8192_rx_ring {
	dma_addr_t dma;
	dma_addr_t dma;
	unsigned int idx;
	unsigned int idx;
	struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
	struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
	/*add for new trx flow*/
	struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
	u16 next_rx_rp; /* next_rx_read_point */
};
};


struct rtl_pci {
struct rtl_pci {
+8 −1
Original line number Original line Diff line number Diff line
@@ -163,6 +163,12 @@
#define DEL_SW_IDX_SZ		30
#define DEL_SW_IDX_SZ		30
#define BAND_NUM			3
#define BAND_NUM			3


/* For now, it's just for 8192ee
 * but not OK yet, keep it 0
 */
#define DMA_IS_64BIT 0
#define RTL8192EE_SEG_NUM		1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */

enum rf_tx_num {
enum rf_tx_num {
	RF_1TX = 0,
	RF_1TX = 0,
	RF_2TX,
	RF_2TX,
@@ -636,6 +642,7 @@ enum rtl_var_map {
	RTL_IMR_VIDOK,		/*AC_VI DMA OK Interrupt */
	RTL_IMR_VIDOK,		/*AC_VI DMA OK Interrupt */
	RTL_IMR_VODOK,		/*AC_VO DMA Interrupt */
	RTL_IMR_VODOK,		/*AC_VO DMA Interrupt */
	RTL_IMR_ROK,		/*Receive DMA OK Interrupt */
	RTL_IMR_ROK,		/*Receive DMA OK Interrupt */
	RTL_IMR_HSISR_IND,	/*HSISR Interrupt*/
	RTL_IBSS_INT_MASKS,	/*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
	RTL_IBSS_INT_MASKS,	/*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
				 * RTL_IMR_TBDER) */
				 * RTL_IMR_TBDER) */
	RTL_IMR_C2HCMD,		/*fw interrupt*/
	RTL_IMR_C2HCMD,		/*fw interrupt*/
@@ -2006,7 +2013,7 @@ struct rtl_intf_ops {
			   struct ieee80211_sta *sta,
			   struct ieee80211_sta *sta,
			   struct sk_buff *skb,
			   struct sk_buff *skb,
			   struct rtl_tcb_desc *ptcb_desc);
			   struct rtl_tcb_desc *ptcb_desc);
	void (*flush)(struct ieee80211_hw *hw, bool drop);
	void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
	int (*reset_trx_ring) (struct ieee80211_hw *hw);
	int (*reset_trx_ring) (struct ieee80211_hw *hw);
	bool (*waitq_insert) (struct ieee80211_hw *hw,
	bool (*waitq_insert) (struct ieee80211_hw *hw,
			      struct ieee80211_sta *sta,
			      struct ieee80211_sta *sta,