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Commit 37a5650b authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Kill has_dp_encoder from pipe_config 



Use the new output_types bitmask instead of has_dp_encoder.
To make it less oainlful provide a small helper
(intel_crtc_has_dp_encoder()) to do the bitsy stuff.

v2: Rebase

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466621833-5054-7-git-send-email-ville.syrjala@linux.intel.com
parent 3d6e9ee0

drivers/gpu/drm/i915/intel_ddi.c

+1 −2
Original line number Diff line number Diff line
@@ -834,7 +834,7 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 
	if (pipe_config->has_pch_encoder)

		dotclock = intel_dotclock_calculate(pipe_config->port_clock,

						    &pipe_config->fdi_m_n);

	else if (pipe_config->has_dp_encoder)

	else if (intel_crtc_has_dp_encoder(pipe_config))

		dotclock = intel_dotclock_calculate(pipe_config->port_clock,

						    &pipe_config->dp_m_n);

	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
@@ -2211,7 +2211,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
		break;

	case TRANS_DDI_MODE_SELECT_DP_SST:

	case TRANS_DDI_MODE_SELECT_DP_MST:

		pipe_config->has_dp_encoder = true;

		pipe_config->lane_count =

			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;

		intel_dp_get_m_n(intel_crtc, pipe_config);

drivers/gpu/drm/i915/intel_display.c

+10 −11
Original line number Diff line number Diff line
@@ -4109,7 +4109,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) 
	intel_fdi_normal_train(crtc);



	/* For PCH DP, enable TRANS_DP_CTL */

	if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {

	if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {

		const struct drm_display_mode *adjusted_mode =

			&intel_crtc->config->base.adjusted_mode;

		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
@@ -4735,7 +4735,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	if (intel_crtc->config->has_pch_encoder)

		intel_prepare_shared_dpll(intel_crtc);



	if (intel_crtc->config->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(intel_crtc->config))

		intel_dp_set_m_n(intel_crtc, M1_N1);



	intel_set_pipe_timings(intel_crtc);
@@ -4826,7 +4826,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) 
	if (intel_crtc->config->shared_dpll)

		intel_enable_shared_dpll(intel_crtc);



	if (intel_crtc->config->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(intel_crtc->config))

		intel_dp_set_m_n(intel_crtc, M1_N1);



	if (!intel_crtc->config->has_dsi_encoder)
@@ -6129,7 +6129,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
	if (WARN_ON(intel_crtc->active))

		return;



	if (intel_crtc->config->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(intel_crtc->config))

		intel_dp_set_m_n(intel_crtc, M1_N1);



	intel_set_pipe_timings(intel_crtc);
@@ -6202,7 +6202,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 


	i9xx_set_pll_dividers(intel_crtc);



	if (intel_crtc->config->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(intel_crtc->config))

		intel_dp_set_m_n(intel_crtc, M1_N1);



	intel_set_pipe_timings(intel_crtc);
@@ -7373,7 +7373,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, 
		vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),

				 0x00d0000f);



	if (pipe_config->has_dp_encoder) {

	if (intel_crtc_has_dp_encoder(pipe_config)) {

		/* Use SSC source */

		if (pipe == PIPE_A)

			vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
@@ -7590,7 +7590,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, 
	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

		dpll |= DPLL_SDVO_HIGH_SPEED;



	if (crtc_state->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(crtc_state))

		dpll |= DPLL_SDVO_HIGH_SPEED;



	/* compute bitmask from p1 value */
@@ -8935,7 +8935,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, 
	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

		dpll |= DPLL_SDVO_HIGH_SPEED;



	if (crtc_state->has_dp_encoder)

	if (intel_crtc_has_dp_encoder(crtc_state))

		dpll |= DPLL_SDVO_HIGH_SPEED;



	/* compute bitmask from p1 value */
@@ -12238,14 +12238,14 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,

		      pipe_config->fdi_m_n.tu);

	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",

		      pipe_config->has_dp_encoder,

		      intel_crtc_has_dp_encoder(pipe_config),

		      pipe_config->lane_count,

		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,

		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,

		      pipe_config->dp_m_n.tu);



	DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",

		      pipe_config->has_dp_encoder,

		      intel_crtc_has_dp_encoder(pipe_config),

		      pipe_config->lane_count,

		      pipe_config->dp_m2_n2.gmch_m,

		      pipe_config->dp_m2_n2.gmch_n,
@@ -12773,7 +12773,6 @@ intel_pipe_config_compare(struct drm_device *dev, 
	PIPE_CONF_CHECK_I(fdi_lanes);

	PIPE_CONF_CHECK_M_N(fdi_m_n);



	PIPE_CONF_CHECK_I(has_dp_encoder);

	PIPE_CONF_CHECK_I(lane_count);

	PIPE_CONF_CHECK_X(lane_lat_optim_mask);

drivers/gpu/drm/i915/intel_dp.c

+0 −3
Original line number Diff line number Diff line
@@ -1501,7 +1501,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)

		pipe_config->has_pch_encoder = true;



	pipe_config->has_dp_encoder = true;

	pipe_config->has_drrs = false;

	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
@@ -2442,8 +2441,6 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 
	    !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)

		pipe_config->limited_color_range = true;



	pipe_config->has_dp_encoder = true;



	pipe_config->lane_count =

		((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

drivers/gpu/drm/i915/intel_dp_mst.c

+0 −3
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 


	pipe_config->dp_encoder_is_mst = true;

	pipe_config->has_pch_encoder = false;

	pipe_config->has_dp_encoder = true;

	bpp = 24;

	/*

	 * for MST we always configure max link bw - the spec doesn't
@@ -246,8 +245,6 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	u32 temp, flags = 0;



	pipe_config->has_dp_encoder = true;



	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	if (temp & TRANS_DDI_PHSYNC)

		flags |= DRM_MODE_FLAG_PHSYNC;

drivers/gpu/drm/i915/intel_drv.h

+8 −4
Original line number Diff line number Diff line
@@ -522,10 +522,6 @@ struct intel_crtc_state { 
	 */

	bool limited_color_range;



	/* DP has a bunch of special case unfortunately, so mark the pipe

	 * accordingly. */

	bool has_dp_encoder;



	/* DSI has special cases */

	bool has_dsi_encoder;
@@ -1198,6 +1194,14 @@ intel_crtc_has_type(const struct intel_crtc_state *crtc_state, 
{

	return crtc_state->output_types & (1 << type);

}

static inline bool

intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)

{

	return crtc_state->output_types &

		((1 << INTEL_OUTPUT_DISPLAYPORT) |

		 (1 << INTEL_OUTPUT_DP_MST) |

		 (1 << INTEL_OUTPUT_EDP));

}

static inline void

intel_wait_for_vblank(struct drm_device *dev, int pipe)

{