Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3770821f authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits 



The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.

Fixes: 11551005 ("clk: rockchip: add clock controller for the RK3399")
Reported-by: default avatarChris Zhong <zyw@rock-chips.com>
Tested-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 6e3732a2

drivers/clk/rockchip/clk-rk3399.c

+1 −1
Original line number Diff line number Diff line
@@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKGATE_CON(8), 15, GFLAGS),



	COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,

			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,

			RK3399_CLKGATE_CON(10), 6, GFLAGS),

	/* i2s */

	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,