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Commit 37655fae authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'v4.6-rockchip-clk2' of... 

Merge tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Pull second batch of rockchip clk updates from Heiko Stuebner:

Inclusion of the rk3368 fractional dividers into our handling scheme,
fixes for missing error-handling in mmc-phase, inverters and cpu-clocks
and some more clock-ids.

* tag 'v4.6-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: include downstream muxes into fractional dividers on rk3368
  clk: rockchip: set the clock ids for RK3228 HDMI
  clk: rockchip: set the clock ids for RK3228 VOP
  clk: rockchip: add the tsadc clocks found on rk3228 SoCs
  clk: rockchip: add the new clock ids for RK3228 HDMI
  clk: rockchip: add the new clock ids for RK3228 VOP
  clk: rockchip: add id of the tsadc clock found on rk3228 SoCs
  clk: rockchip: fix coding style for clk-cpu.c
  clk: rockchip: don't return NULL when registering mmc branch fails
  clk: rockchip: don't return NULL when registering inverter fails
  clk: rockchip: check grf when waiting pll lock
  clk: rockchip: disable alt_parent clk in err cases when registering cpuclk
parents 8626556f 7af8a26c

drivers/clk/rockchip/clk-cpu.c

+5 −3
Original line number Diff line number Diff line
@@ -290,14 +290,14 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 
		pr_err("%s: could not lookup parent clock %s\n",

		       __func__, parent_names[0]);

		ret = -EINVAL;

		goto free_cpuclk;

		goto free_alt_parent;

	}



	ret = clk_notifier_register(clk, &cpuclk->clk_nb);

	if (ret) {

		pr_err("%s: failed to register clock notifier for %s\n",

				__func__, name);

		goto free_cpuclk;

		goto free_alt_parent;

	}



	if (nrates > 0) {
@@ -326,6 +326,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, 
	kfree(cpuclk->rate_table);

unregister_notifier:

	clk_notifier_unregister(clk, &cpuclk->clk_nb);

free_alt_parent:

	clk_disable_unprepare(cpuclk->alt_parent);

free_cpuclk:

	kfree(cpuclk);

	return ERR_PTR(ret);

drivers/clk/rockchip/clk-inverter.c

+2 −6
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ struct clk *rockchip_clk_register_inverter(const char *name, 


	inv_clock = kmalloc(sizeof(*inv_clock), GFP_KERNEL);

	if (!inv_clock)

		return NULL;

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.num_parents = num_parents;
@@ -106,11 +106,7 @@ struct clk *rockchip_clk_register_inverter(const char *name, 


	clk = clk_register(NULL, &inv_clock->hw);

	if (IS_ERR(clk))

		goto err_free;

		kfree(inv_clock);



	return clk;



err_free:

	kfree(inv_clock);

	return NULL;

}

drivers/clk/rockchip/clk-mmc-phase.c

+2 −6
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ struct clk *rockchip_clk_register_mmc(const char *name, 


	mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);

	if (!mmc_clock)

		return NULL;

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.num_parents = num_parents;
@@ -172,11 +172,7 @@ struct clk *rockchip_clk_register_mmc(const char *name, 


	clk = clk_register(NULL, &mmc_clock->hw);

	if (IS_ERR(clk))

		goto err_free;

		kfree(mmc_clock);



	return clk;



err_free:

	kfree(mmc_clock);

	return NULL;

}

drivers/clk/rockchip/clk-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -94,6 +94,11 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) 
	unsigned int val;

	int delay = 24000000, ret;



	if (IS_ERR(grf)) {

		pr_err("%s: grf regmap not available\n", __func__);

		return PTR_ERR(grf);

	}



	while (delay > 0) {

		ret = regmap_read(grf, pll->lock_offset, &val);

		if (ret) {

drivers/clk/rockchip/clk-rk3228.c

+9 −9
Original line number Diff line number Diff line
@@ -285,7 +285,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
			RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,

			RK2928_CLKGATE_CON(3), 5, GFLAGS),



	GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,

	GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,

			RK2928_CLKGATE_CON(3), 7, GFLAGS),



	COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
@@ -364,11 +364,11 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(3), 1, GFLAGS),

	MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,

			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),

	DIV(0, "dclk_hdmiphy", "sclk_vop_src", 0,

	DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,

			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),

	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,

			RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),

	MUX(0, "dclk_vop", mux_dclk_vop_p, 0,

	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,

			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),



	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -424,7 +424,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	GATE(0, "sclk_otgphy1", "xin24m", 0,

			RK2928_CLKGATE_CON(1), 6, GFLAGS),



	COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,

	COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,

			RK2928_CLKSEL_CON(24), 6, 10, DFLAGS,

			RK2928_CLKGATE_CON(2), 8, GFLAGS),
@@ -505,7 +505,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),

	GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),



	GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),

	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),

	GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),



	GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
@@ -513,13 +513,13 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 


	GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),

	GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),

	GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),

	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),

	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),

	GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),

	GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),

	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),

	GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),

	GATE(0, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),

	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),

	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),

	GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
@@ -584,7 +584,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 
	GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 12, GFLAGS),

	GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 13, GFLAGS),

	GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 14, GFLAGS),

	GATE(0, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),

	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 15, GFLAGS),

	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 0, GFLAGS),

	GATE(0, "pclk_cru", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),

	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
@@ -592,7 +592,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { 


	GATE(0, "pclk_ddrphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 3, GFLAGS),

	GATE(0, "pclk_acodecphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 5, GFLAGS),

	GATE(0, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),

	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),

	GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),

	GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),