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Commit 370b9910 authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

drm/msm/sde: add 12 stage blending support 



Increase the supported LM stages to support 12 stage blending.
Remove the hard-coding of blend_op offset and LM pair-mask. Add
parsing logic to get the data from the device tree and add
these entries for msmskunk target.

Change-Id: I10690ab7f82015b74ad1f78e0d9e20f468858b76
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent 3171ff8f

Documentation/devicetree/bindings/display/msm/sde.txt

+10 −0
Original line number Diff line number Diff line
@@ -66,6 +66,11 @@ Required properties 
				from "mdp_phys" defined in reg property. The number

				of offsets defined should reflect the number of

				programmable interface blocks available in hardware.

- qcom,sde-mixer-blend-op-off	Array of offset addresses for the available

				blending stages. The offsets are relative to

				qcom,sde-mixer-off.

- qcom,sde-mixer-pair-mask	Array of mixer numbers that can be paired with

				mixer number corresponding to the array index.



Optional properties:

- clock-rate:		List of clock rates in Hz.
@@ -311,6 +316,11 @@ Example: 
    qcom,sde-dsc-off = <0x00081000 0x00081400>;

    qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;



    qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;

    qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

				    0xb0 0xc8 0xe0 0xf8 0x110>;





    qcom,sde-sspp-type = "vig", "vig", "vig",

			      "vig", "rgb", "rgb",

			      "rgb", "rgb", "dma",

arch/arm64/boot/dts/qcom/msmskunk-sde.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -54,6 +54,11 @@ 
		qcom,sde-sspp-xin-id = <0 4 8 12

					1 5 9 13>;



		qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;



		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

						0xb0 0xc8 0xe0 0xf8 0x110>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl =

				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+47 −9
Original line number Diff line number Diff line
@@ -192,6 +192,7 @@ enum { 
enum {

	MIXER_OFF,

	MIXER_LEN,

	MIXER_PAIR_MASK,

	MIXER_BLOCKS,

	MIXER_PROP_MAX,

};
@@ -201,6 +202,11 @@ enum { 
	MIXER_BLOCKS_PROP_MAX,

};



enum {

	MIXER_BLEND_OP_OFF,

	MIXER_BLEND_PROP_MAX,

};



enum {

	WB_OFF,

	WB_LEN,
@@ -309,9 +315,16 @@ static struct sde_prop_type ctl_prop[] = { 
	{HW_LEN, "qcom,sde-ctl-size", false, PROP_TYPE_U32},

};



struct sde_prop_type mixer_blend_prop[] = {

	{MIXER_BLEND_OP_OFF, "qcom,sde-mixer-blend-op-off", true,

		PROP_TYPE_U32_ARRAY},

};



static struct sde_prop_type mixer_prop[] = {

	{MIXER_OFF, "qcom,sde-mixer-off", true, PROP_TYPE_U32_ARRAY},

	{MIXER_LEN, "qcom,sde-mixer-size", false, PROP_TYPE_U32},

	{MIXER_PAIR_MASK, "qcom,sde-mixer-pair-mask", true,

		PROP_TYPE_U32_ARRAY},

	{MIXER_BLOCKS, "qcom,sde-mixer-blocks", false, PROP_TYPE_NODE},

};
@@ -1002,14 +1015,15 @@ static int sde_ctl_parse_dt(struct device_node *np, 
static int sde_mixer_parse_dt(struct device_node *np,

						struct sde_mdss_cfg *sde_cfg)

{

	int rc, prop_count[MIXER_PROP_MAX], i;

	int rc, prop_count[MIXER_PROP_MAX], i, j;

	int blocks_prop_count[MIXER_BLOCKS_PROP_MAX];

	int blend_prop_count[MIXER_BLEND_PROP_MAX];

	bool prop_exists[MIXER_PROP_MAX];

	bool blocks_prop_exists[MIXER_BLOCKS_PROP_MAX];

	bool blend_prop_exists[MIXER_BLEND_PROP_MAX];

	struct sde_prop_value *prop_value = NULL, *blocks_prop_value = NULL;

	u32 off_count, max_blendstages;

	u32 blend_reg_base[] = {0x20, 0x50, 0x80, 0xb0, 0x230, 0x260, 0x290};

	u32 lm_pair_mask[] = {LM_1, LM_0, LM_5, 0x0, 0x0, LM_2};

	struct sde_prop_value *blend_prop_value = NULL;

	u32 off_count, blend_off_count, max_blendstages, lm_pair_mask;

	struct sde_lm_cfg *mixer;

	struct sde_lm_sub_blks *sblk;

	int pp_count, dspp_count;
@@ -1065,6 +1079,24 @@ static int sde_mixer_parse_dt(struct device_node *np, 
				blocks_prop_value);

	}



	/* get the blend_op register offsets */

	blend_prop_value = kzalloc(MIXER_BLEND_PROP_MAX *

			sizeof(struct sde_prop_value), GFP_KERNEL);

	if (!blend_prop_value) {

		rc = -ENOMEM;

		goto end;

	}

	rc = _validate_dt_entry(np, mixer_blend_prop,

		ARRAY_SIZE(mixer_blend_prop), blend_prop_count,

		&blend_off_count);

	if (rc)

		goto end;



	rc = _read_dt_entry(np, mixer_blend_prop, ARRAY_SIZE(mixer_blend_prop),

		blend_prop_count, blend_prop_exists, blend_prop_value);

	if (rc)

		goto end;



	for (i = 0, pp_idx = 0, dspp_idx = 0; i < off_count; i++) {

		mixer = sde_cfg->mixer + i;

		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
@@ -1081,14 +1113,19 @@ static int sde_mixer_parse_dt(struct device_node *np, 
		if (!prop_exists[MIXER_LEN])

			mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;



		if (lm_pair_mask[i])

			mixer->lm_pair_mask = 1 << lm_pair_mask[i];

		lm_pair_mask = PROP_VALUE_ACCESS(prop_value,

				MIXER_PAIR_MASK, i);

		if (lm_pair_mask)

			mixer->lm_pair_mask = 1 << lm_pair_mask;



		sblk->maxblendstages = max_blendstages;

		sblk->maxwidth = sde_cfg->max_mixer_width;

		memcpy(sblk->blendstage_base, blend_reg_base, sizeof(u32) *

			min_t(u32, MAX_BLOCKS, min_t(u32,

			ARRAY_SIZE(blend_reg_base), max_blendstages)));



		for (j = 0; j < blend_off_count; j++)

			sblk->blendstage_base[j] =

				PROP_VALUE_ACCESS(blend_prop_value,

						MIXER_BLEND_OP_OFF, j);



		if (sde_cfg->has_src_split)

			set_bit(SDE_MIXER_SOURCESPLIT, &mixer->features);

		if (sde_cfg->has_dim_layer)
@@ -1122,6 +1159,7 @@ static int sde_mixer_parse_dt(struct device_node *np, 
end:

	kfree(prop_value);

	kfree(blocks_prop_value);

	kfree(blend_prop_value);

	return rc;

}

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+4 −0
Original line number Diff line number Diff line
@@ -131,6 +131,10 @@ enum sde_stage { 
	SDE_STAGE_4,

	SDE_STAGE_5,

	SDE_STAGE_6,

	SDE_STAGE_7,

	SDE_STAGE_8,

	SDE_STAGE_9,

	SDE_STAGE_10,

	SDE_STAGE_MAX

};

enum sde_dspp {