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Commit 361f7d17 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 core platform updates from Ingo Molnar:
 "The main changes are:

   - Intel Atom platform updates.  (Andy Shevchenko)

   - modularity fixlets.  (Paul Gortmaker)

   - x86 platform clockevents driver updates for lguest, uv and Xen.
     (Viresh Kumar)

   - Microsoft Hyper-V TSC fixlet.  (Vitaly Kuznetsov)"

* 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/platform: Make atom/pmc_atom.c explicitly non-modular
  x86/hyperv: Mark the Hyper-V TSC as unstable
  x86/xen/time: Migrate to new set-state interface
  x86/uv/time: Migrate to new set-state interface
  x86/lguest/timer: Migrate to new set-state interface
  x86/pci/intel_mid_pci: Use proper constants for irq polarity
  x86/pci/intel_mid_pci: Make intel_mid_pci_ops static
  x86/pci/intel_mid_pci: Propagate actual return code
  x86/pci/intel_mid_pci: Work around for IRQ0 assignment
  x86/platform/iosf_mbi: Add Intel Tangier PCI id
  x86/platform/iosf_mbi: Source cleanup
  x86/platform/iosf_mbi: Remove NULL pointer checks for pci_dev_put()
  x86/platform/iosf_mbi: Check return value of debugfs_create properly
  x86/platform/iosf_mbi: Move to dedicated folder
  x86/platform/intel/pmc_atom: Move the PMC-Atom code to arch/x86/platform/atom
  x86/platform/intel/pmc_atom: Add Cherrytrail PMC interface
  x86/platform/intel/pmc_atom: Supply register mappings via PMC object
  x86/platform/intel/pmc_atom: Print index of device in loop
  x86/platform/intel/pmc_atom: Export accessors to PMC registers
parents 25525bea e971aa2c

arch/x86/include/asm/pmc_atom.h

+29 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 


/* ValleyView Power Control Unit PCI Device ID */

#define	PCI_DEVICE_ID_VLV_PMC	0x0F1C

/* CherryTrail Power Control Unit PCI Device ID */

#define	PCI_DEVICE_ID_CHT_PMC	0x229C



/* PMC Memory mapped IO registers */

#define	PMC_BASE_ADDR_OFFSET	0x44
@@ -29,6 +31,10 @@ 
#define	PMC_FUNC_DIS		0x34

#define	PMC_FUNC_DIS_2		0x38



/* CHT specific bits in FUNC_DIS2 register */

#define	BIT_FD_GMM		BIT(3)

#define	BIT_FD_ISH		BIT(4)



/* S0ix wake event control */

#define	PMC_S0IX_WAKE_EN	0x3C
@@ -75,6 +81,21 @@ 
#define PMC_PSS_BIT_USB			BIT(16)

#define PMC_PSS_BIT_USB_SUS		BIT(17)



/* CHT specific bits in PSS register */

#define	PMC_PSS_BIT_CHT_UFS		BIT(7)

#define	PMC_PSS_BIT_CHT_UXD		BIT(11)

#define	PMC_PSS_BIT_CHT_UXD_FD		BIT(12)

#define	PMC_PSS_BIT_CHT_UX_ENG		BIT(15)

#define	PMC_PSS_BIT_CHT_USB_SUS		BIT(16)

#define	PMC_PSS_BIT_CHT_GMM		BIT(17)

#define	PMC_PSS_BIT_CHT_ISH		BIT(18)

#define	PMC_PSS_BIT_CHT_DFX_MASTER	BIT(26)

#define	PMC_PSS_BIT_CHT_DFX_CLUSTER1	BIT(27)

#define	PMC_PSS_BIT_CHT_DFX_CLUSTER2	BIT(28)

#define	PMC_PSS_BIT_CHT_DFX_CLUSTER3	BIT(29)

#define	PMC_PSS_BIT_CHT_DFX_CLUSTER4	BIT(30)

#define	PMC_PSS_BIT_CHT_DFX_CLUSTER5	BIT(31)



/* These registers reflect D3 status of functions */

#define	PMC_D3_STS_0		0xA0
@@ -117,6 +138,10 @@ 
#define	BIT_USH_SS_PHY		BIT(2)

#define	BIT_DFX			BIT(3)



/* CHT specific bits in PMC_D3_STS_1 register */

#define	BIT_STS_GMM		BIT(1)

#define	BIT_STS_ISH		BIT(2)



/* PMC I/O Registers */

#define	ACPI_BASE_ADDR_OFFSET	0x40

#define	ACPI_BASE_ADDR_MASK	0xFFFFFE00
@@ -126,4 +151,8 @@ 
#define	SLEEP_TYPE_MASK		0xFFFFECFF

#define	SLEEP_TYPE_S5		0x1C00

#define	SLEEP_ENABLE		0x2000



extern int pmc_atom_read(int offset, u32 *value);

extern int pmc_atom_write(int offset, u32 value);



#endif /* PMC_ATOM_H */

arch/x86/kernel/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -109,8 +109,6 @@ obj-$(CONFIG_EFI) += sysfb_efi.o 


obj-$(CONFIG_PERF_EVENTS)		+= perf_regs.o

obj-$(CONFIG_TRACING)			+= tracepoint.o

obj-$(CONFIG_IOSF_MBI)			+= iosf_mbi.o

obj-$(CONFIG_PMC_ATOM)			+= pmc_atom.o



###

# 64 bit specific files

arch/x86/kernel/cpu/mshyperv.c

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ static void __init ms_hyperv_init_platform(void) 


	machine_ops.shutdown = hv_machine_shutdown;

	machine_ops.crash_shutdown = hv_machine_crash_shutdown;

	mark_tsc_unstable("running on Hyper-V");

}



const __refconst struct hypervisor_x86 x86_hyper_ms_hyperv = {

arch/x86/lguest/boot.c

+6 −18
Original line number Diff line number Diff line
@@ -985,23 +985,11 @@ static int lguest_clockevent_set_next_event(unsigned long delta, 
	return 0;

}



static void lguest_clockevent_set_mode(enum clock_event_mode mode,

                                      struct clock_event_device *evt)

static int lguest_clockevent_shutdown(struct clock_event_device *evt)

{

	switch (mode) {

	case CLOCK_EVT_MODE_UNUSED:

	case CLOCK_EVT_MODE_SHUTDOWN:

	/* A 0 argument shuts the clock down. */

	hcall(LHCALL_SET_CLOCKEVENT, 0, 0, 0, 0);

		break;

	case CLOCK_EVT_MODE_ONESHOT:

		/* This is what we expect. */

		break;

	case CLOCK_EVT_MODE_PERIODIC:

		BUG();

	case CLOCK_EVT_MODE_RESUME:

		break;

	}

	return 0;

}



/* This describes our primitive timer chip. */
@@ -1009,7 +997,7 @@ static struct clock_event_device lguest_clockevent = { 
	.name                   = "lguest",

	.features               = CLOCK_EVT_FEAT_ONESHOT,

	.set_next_event         = lguest_clockevent_set_next_event,

	.set_mode               = lguest_clockevent_set_mode,

	.set_state_shutdown	= lguest_clockevent_shutdown,

	.rating                 = INT_MAX,

	.mult                   = 1,

	.shift                  = 0,

arch/x86/pci/intel_mid_pci.c

+29 −7
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ 


#define PCIE_CAP_OFFSET	0x100



/* Quirks for the listed devices */

#define PCI_DEVICE_ID_INTEL_MRFL_MMC	0x1190



/* Fixed BAR fields */

#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */

#define PCI_FIXED_BAR_0_SIZE	0x04
@@ -210,22 +213,41 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) 
{

	struct irq_alloc_info info;

	int polarity;

	int ret;



	if (pci_has_managed_irq(dev))

		return 0;



	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)

		polarity = 0; /* active high */

	else

		polarity = 1; /* active low */

	switch (intel_mid_identify_cpu()) {

	case INTEL_MID_CPU_CHIP_TANGIER:

		polarity = IOAPIC_POL_HIGH;



		/* Special treatment for IRQ0 */

		if (dev->irq == 0) {

			/*

			 * TNG has IRQ0 assigned to eMMC controller. But there

			 * are also other devices with bogus PCI configuration

			 * that have IRQ0 assigned. This check ensures that

			 * eMMC gets it.

			 */

			if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)

				return -EBUSY;

		}

		break;

	default:

		polarity = IOAPIC_POL_LOW;

		break;

	}



	ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);



	/*

	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to

	 * IOAPIC RTE entries, so we just enable RTE for the device.

	 */

	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)

		return -EBUSY;

	ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);

	if (ret < 0)

		return ret;



	dev->irq_managed = 1;
@@ -244,7 +266,7 @@ static void intel_mid_pci_irq_disable(struct pci_dev *dev) 
	}

}



struct pci_ops intel_mid_pci_ops = {

static struct pci_ops intel_mid_pci_ops = {

	.read = pci_read,

	.write = pci_write,

};