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Commit 3598706b authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
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drm/i915: avoid premature DP AUX timeouts 

During DP AUX communication we might time out 1 jiffy too early, because
the calculated expiry jiffy value is one less than needed.

This is only one reason for false DP AUX timeouts. For a complete
solution we also need the following fix, which is now queued for
mainline: http://marc.info/?l=linux-kernel&m=136748515710837&w=2

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64133



Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e054cc39

drivers/gpu/drm/i915/intel_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -303,7 +303,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) 
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)

	if (has_aux_irq)

		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,

					  msecs_to_jiffies(10));

					  msecs_to_jiffies_timeout(10));

	else

		done = wait_for_atomic(C, 10) == 0;

	if (!done)

drivers/gpu/drm/i915/intel_i2c.c

+2 −1
Original line number Diff line number Diff line
@@ -263,7 +263,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) 
	/* Important: The hw handles only the first bit, so set only one! */

	I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);



	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);

	ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,

				 msecs_to_jiffies_timeout(10));



	I915_WRITE(GMBUS4 + reg_offset, 0);