[MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board (355c471f) · Commits · e / devices / android_kernel_fairphone_FP3

arch/mips/Kconfig

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		@@ -530,6 +530,20 @@ config QEMU
		simulate actual MIPS hardware platforms. More information on Qemu
		can be found at http://www.linux-mips.org/wiki/Qemu.

		config MARKEINS
		bool "Support for NEC EMMA2RH Mark-eins"
		select DMA_NONCOHERENT
		select HW_HAS_PCI
		select IRQ_CPU
		select SWAP_IO_SPACE
		select SYS_SUPPORTS_32BIT_KERNEL
		select SYS_SUPPORTS_BIG_ENDIAN
		select SYS_SUPPORTS_LITTLE_ENDIAN
		select SYS_HAS_CPU_R5000
		help
		This enables support for the R5432-based NEC Mark-eins
		boards with R5500 CPU.

		config SGI_IP22
		bool "SGI IP22 (Indy/Indigo2)"
		select ARC
		@@ -968,6 +982,11 @@ config SOC_PNX8550
		config SWAP_IO_SPACE
		bool

		config EMMA2RH
		bool
		depends on MARKEINS
		default y

		#
		# Unfortunately not all GT64120 systems run the chip at the same clock.
		# As the user for the clock rate and try to minimize the available options.

arch/mips/Makefile

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		@@ -465,6 +465,15 @@ libs-$(CONFIG_PNX8550_JBS) += arch/mips/philips/pnx8550/jbs/
		#cflags-$(CONFIG_PNX8550_JBS) += -Iinclude/asm-mips/mach-pnx8550
		load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000

		# NEC EMMA2RH boards
		#
		core-$(CONFIG_EMMA2RH) += arch/mips/emma2rh/common/
		cflags-$(CONFIG_EMMA2RH) += -Iinclude/asm-mips/mach-emma2rh

		# NEC EMMA2RH Mark-eins
		core-$(CONFIG_MARKEINS) += arch/mips/emma2rh/markeins/
		load-$(CONFIG_MARKEINS) += 0xffffffff88100000

		#
		# SGI IP22 (Indy/Indigo2)
		#

arch/mips/configs/emma2rh_defconfig

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File added.

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arch/mips/emma2rh/common/Makefile

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		#
		# arch/mips/emma2rh/common/Makefile
		# Makefile for the common code of NEC EMMA2RH based board.
		#
		# Copyright (C) NEC Electronics Corporation 2005-2006
		#
		# This program is free software; you can redistribute it and/or modify
		# it under the terms of the GNU General Public License as published by
		# the Free Software Foundation; either version 2 of the License, or
		# (at your option) any later version.
		#

		obj-$(CONFIG_MARKEINS) += irq.o irq_emma2rh.o prom.o

arch/mips/emma2rh/common/irq.c

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		/*
		* arch/mips/emma2rh/common/irq.c
		* This file is common irq dispatcher.
		*
		* Copyright (C) NEC Electronics Corporation 2005-2006
		*
		* This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c
		*
		* Copyright 2001 MontaVista Software Inc.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		*/
		#include <linux/config.h>
		#include <linux/init.h>
		#include <linux/interrupt.h>
		#include <linux/irq.h>
		#include <linux/types.h>

		#include <asm/i8259.h>
		#include <asm/system.h>
		#include <asm/mipsregs.h>
		#include <asm/debug.h>
		#include <asm/addrspace.h>
		#include <asm/bootinfo.h>

		#include <asm/emma2rh/emma2rh.h>

		/*
		* the first level int-handler will jump here if it is a emma2rh irq
		*/
		asmlinkage void emma2rh_irq_dispatch(struct pt_regs *regs)
		{
		u32 intStatus;
		u32 bitmask;
		u32 i;

		intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0)
		& emma2rh_in32(EMMA2RH_BHIF_INT_EN_0);

		#ifdef EMMA2RH_SW_CASCADE
		if (intStatus &
		(1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
		u32 swIntStatus;
		swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT)
		& emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN);
		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
		if (swIntStatus & bitmask) {
		do_IRQ(EMMA2RH_SW_IRQ_BASE + i, regs);
		return;
		}
		}
		}
		#endif

		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
		if (intStatus & bitmask) {
		do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
		return;
		}
		}

		intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1)
		& emma2rh_in32(EMMA2RH_BHIF_INT_EN_1);

		#ifdef EMMA2RH_GPIO_CASCADE
		if (intStatus &
		(1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) {
		u32 gpioIntStatus;
		gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST)
		& emma2rh_in32(EMMA2RH_GPIO_INT_MASK);
		for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) {
		if (gpioIntStatus & bitmask) {
		do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i, regs);
		return;
		}
		}
		}
		#endif

		for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) {
		if (intStatus & bitmask) {
		do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
		return;
		}
		}

		intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2)
		& emma2rh_in32(EMMA2RH_BHIF_INT_EN_2);

		for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) {
		if (intStatus & bitmask) {
		do_IRQ(EMMA2RH_IRQ_BASE + i, regs);
		return;
		}
		}
		}