Merge "drivers: llcc: add support to detect llcc instances dynamically"

#define LLCC_STATUS_READ_DELAY 100

#define CACHE_LINE_SIZE_SHIFT 6

#define SIZE_PER_LLCC_SHIFT   2

#define LLCC_COMMON_STATUS0		0x0003000C

#define LLCC_LB_CNT_MASK		0xf0000000

#define LLCC_LB_CNT_SHIFT		28

#define MAX_CAP_TO_BYTES(n) (n * 1024)

#define LLCC_TRP_ACT_CTRLn(n) (n * 0x1000)

	u32 llcc_config_data_sz;

	u32 max_slices;

	u32 b_off;

	u32 no_banks;

	unsigned long *llcc_slice_map;

};

		attr1_val |= (llcc_table[i].priority << ATTR1_PRIORITY_SHIFT);

		max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);

		max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;

		/* There are four llcc instances llcc0..llcc3. The SW writes to

		 * to broadcast register which gets propagated to each llcc.

		/* LLCC instances can vary for each target.

		 * The SW writes to broadcast register which gets propagated

		 * to each llcc instace (llcc0,.. llccN).

		 * Since the size of the memory is divided equally amongst the

		 * four llcc, we need to divide the max cap by 4

		 * llcc instances, we need to configure the max cap accordingly.

		 */

		max_cap_cacheline >>= SIZE_PER_LLCC_SHIFT;

		max_cap_cacheline = (max_cap_cacheline / drv->no_banks);

		max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;

		attr1_val |= (max_cap_cacheline << ATTR1_MAX_CAP_SHIFT);

		attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;

		      const struct llcc_slice_config *llcc_cfg, u32 sz)

{

	int rc = 0;

	u32 num_banks = 0;

	struct device *dev = &pdev->dev;

	static struct llcc_drv_data *drv_data;

	if (!drv_data->llcc_map)

		return PTR_ERR(drv_data->llcc_map);

	regmap_read(drv_data->llcc_map, LLCC_COMMON_STATUS0,

		    &num_banks);

	num_banks &= LLCC_LB_CNT_MASK;

	num_banks >>= LLCC_LB_CNT_SHIFT;

	drv_data->no_banks = num_banks;

	rc = of_property_read_u32(pdev->dev.of_node, "max-slices",

				  &drv_data->max_slices);

	if (rc) {