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Commit 34acb090 authored by dmitry pervushin's avatar dmitry pervushin Committed by Russell King
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[ARM] 5468/1: Freescale STMP platform support [3/10] 



Minimal definition of register set for 37xx boards

Signed-off-by: default avatardmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 1e3dd535

arch/arm/mach-stmp37xx/include/mach/regs-apbh.h

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/*

 * STMP APBH Register Definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef _INCLUDE_ASM_ARCH_REGS_APBH_H

#define _INCLUDE_ASM_ARCH_REGS_APBH_H



#include <mach/stmp3xxx_regs.h>



#ifndef REGS_APBH_BASE

#define REGS_APBH_BASE (REGS_BASE + 0x00004000)

#endif



HW_REGISTER(HW_APBH_CTRL0, REGS_APBH_BASE, 0x00)

#define BP_APBH_CTRL0_SFTRST      31

#define BM_APBH_CTRL0_SFTRST      0x80000000

#define BP_APBH_CTRL0_CLKGATE      30

#define BM_APBH_CTRL0_CLKGATE      0x40000000

#define BP_APBH_CTRL0_RESET_CHANNEL      16

#define BM_APBH_CTRL0_RESET_CHANNEL      0x00FF0000

#define BF_APBH_CTRL0_RESET_CHANNEL(v)   \

	(((v) << BP_APBH_CTRL0_RESET_CHANNEL) & BM_APBH_CTRL0_RESET_CHANNEL)

HW_REGISTER(HW_APBH_CTRL1, REGS_APBH_BASE, 0x10)

#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      9

#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN      0x00000200

#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      8

#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN      0x00000100

#define BP_APBH_CTRL1_CH7_CMDCMPLT_IRQ      7

#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ      0x00000080

#define BP_APBH_CTRL1_CH1_CMDCMPLT_IRQ      1

#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ      0x00000002

#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0

#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ      0x00000001

#define BP_APBH_CTRL1_CH1_ERR_IRQ	    17

#define BM_APBH_CTRL1_CH1_ERR_IRQ	   0x00020000

HW_REGISTER_0(HW_APBH_DEVSEL, REGS_APBH_BASE, 0x20)

HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CURCMDAR, REGS_APBH_BASE, 0x40, 0x70)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_NXTCMDAR, REGS_APBH_BASE, 0x50, 0x70)

#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR      0

#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR      0xFFFFFFFF

#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v)   ((u32) v)

HW_REGISTER_RO_INDEXED(HW_APBH_CHn_CMD, REGS_APBH_BASE, 0x60, 0x70)

#define BM_APBH_CHn_CMD_XFER_COUNT		0xFFFF0000

#define BP_APBH_CHn_CMD_XFER_COUNT		16

#define BF_APBH_CHn_CMD_XFER_COUNT(v)		\

	(((v) << BP_APBH_CHn_CMD_XFER_COUNT) & BM_APBH_CHn_CMD_XFER_COUNT)

#define BM_APBH_CHn_CMD_CMDWORDS		0x0000F000

#define BP_APBH_CHn_CMD_CMDWORDS		12

#define BF_APBH_CHn_CMD_CMDWORDS(v)		\

	(((v) << BP_APBH_CHn_CMD_CMDWORDS) & BM_APBH_CHn_CMD_CMDWORDS)

#define BM_APBH_CHn_CMD_WAIT4ENDCMD		0x00000080

#define BM_APBH_CHn_CMD_SEMAPHORE		0x00000040

#define BP_APBH_CHn_CMD_SEMAPHORE		6

#define BF_APBH_CHn_CMD_SEMAPHORE(v)		\

	(((v) << BP_APBH_CHn_CMD_SEMAPHORE) & BM_APBH_CHn_CMD_SEMAPHORE)

#define BM_APBH_CHn_CMD_NANDWAIT4READY	 0x00000020

#define BP_APBH_CHn_CMD_NANDLOCK		4

#define BM_APBH_CHn_CMD_NANDLOCK		0x00000010

#define BF_APBH_CHn_CMD_NANDLOCK(v)		\

	(((v) << BP_APBH_CHn_CMD_NANDLOCK) & BM_APBH_CHn_CMD_NANDLOCK)

#define BM_APBH_CHn_CMD_IRQONCMPLT		0x00000008

#define BM_APBH_CHn_CMD_CHAIN		0x00000004

#define BM_APBH_CHn_CMD_DMA_READ		0x00000003

#define BP_APBH_CHn_CMD_DMA_READ		0

#define BF_APBH_CHn_CMD_DMA_READ(v)		\

	(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)

#define BF_APBH_CHn_CMD_COMMAND(v)		\

	(((v) << BP_APBH_CHn_CMD_DMA_READ) & BM_APBH_CHn_CMD_DMA_READ)

#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER  0x0

#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE    0x1

#define BV_APBH_CHn_CMD_COMMAND__DMA_READ     0x2

#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE    0x3

HW_REGISTER_INDEXED(HW_APBH_CHn_BAR, REGS_APBH_BASE, 0x70, 0x70)

HW_REGISTER_0_INDEXED(HW_APBH_CHn_SEMA, REGS_APBH_BASE, 0x80, 0x70)

#define BP_APBH_CHn_SEMA_INCREMENT_SEMA      0

#define BM_APBH_CHn_SEMA_INCREMENT_SEMA      0x000000FF

#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v)   \

	(((v) << BP_APBH_CHn_SEMA_INCREMENT_SEMA) & \

	BM_APBH_CHn_SEMA_INCREMENT_SEMA)

#define BP_APBH_CHn_SEMA_PHORE      16

#define BM_APBH_CHn_SEMA_PHORE      0x00FF0000

HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG1, REGS_APBH_BASE, 0x90, 0x70)

HW_REGISTER_RO_INDEXED(HW_APBH_CHn_DEBUG2, REGS_APBH_BASE, 0xA0, 0x70)

HW_REGISTER_RO(HW_APBH_VERSION, REGS_APBH_BASE, 0x3F0)



#endif /* _INCLUDE_ASM_ARCH_REGS_APBH_H */

arch/arm/mach-stmp37xx/include/mach/regs-apbx.h

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/*

 * STMP APBX Register Definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef _INCLUDE_ASM_ARCH_REGS_APBX_H

#define _INCLUDE_ASM_ARCH_REGS_APBX_H



#include <mach/stmp3xxx_regs.h>



#ifndef REGS_APBX_BASE

#define REGS_APBX_BASE (REGS_BASE + 0x00024000)

#endif



HW_REGISTER(HW_APBX_CTRL0, REGS_APBX_BASE, 0x00)

#define BP_APBX_CTRL0_SFTRST      31

#define BM_APBX_CTRL0_SFTRST      0x80000000

#define BP_APBX_CTRL0_CLKGATE      30

#define BM_APBX_CTRL0_CLKGATE      0x40000000

#define BP_APBX_CTRL0_RESET_CHANNEL      16

#define BM_APBX_CTRL0_RESET_CHANNEL      0x00FF0000

#define BF_APBX_CTRL0_RESET_CHANNEL(v)   \

	(((v) << BP_APBX_CTRL0_RESET_CHANNEL) & BM_APBX_CTRL0_RESET_CHANNEL)

HW_REGISTER(HW_APBX_CTRL1, REGS_APBX_BASE, 0x10)

HW_REGISTER_0(HW_APBX_DEVSEL, REGS_APBX_BASE, 0x20)

#define BP_APBX_DEVSEL_CH7      28

#define BM_APBX_DEVSEL_CH7      0xF0000000

#define BF_APBX_DEVSEL_CH7(v)   \

	(((v) << BP_APBX_DEVSEL_CH7) & BM_APBX_DEVSEL_CH7)

#define BV_APBX_DEVSEL_CH7__USE_UART  0x0

#define BV_APBX_DEVSEL_CH7__USE_IRDA  0x1

#define BP_APBX_DEVSEL_CH6	24

#define BM_APBX_DEVSEL_CH6      0x0F000000

#define BF_APBX_DEVSEL_CH6(v)   \

	(((v) << BP_APBX_DEVSEL_CH6) & BM_APBX_DEVSEL_CH6)

#define BV_APBX_DEVSEL_CH6__USE_UART  0x0

#define BV_APBX_DEVSEL_CH6__USE_IRDA  0x1

#define BP_APBX_CTRL1_CH7_AHB_ERROR_IRQ      23

#define BM_APBX_CTRL1_CH7_AHB_ERROR_IRQ      0x00800000

#define BP_APBX_CTRL1_CH6_AHB_ERROR_IRQ      22

#define BM_APBX_CTRL1_CH6_AHB_ERROR_IRQ      0x00400000

#define BP_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN      15

#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN      0x00008000

#define BP_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN      14

#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN      0x00004000



HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CURCMDAR, REGS_APBX_BASE, 0x40, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_NXTCMDAR, REGS_APBX_BASE, 0x50, 0x70)

#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR      0

#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR      0xFFFFFFFF

#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v)   ((u32) v)

HW_REGISTER_RO_INDEXED(HW_APBX_CHn_CMD, REGS_APBX_BASE, 0x60, 0x70)

#define BP_APBX_CHn_CMD_XFER_COUNT      16

#define BM_APBX_CHn_CMD_XFER_COUNT      0xFFFF0000

#define BF_APBX_CHn_CMD_XFER_COUNT(v)   \

	(((v) << BP_APBX_CHn_CMD_XFER_COUNT) & BM_APBX_CHn_CMD_XFER_COUNT)

#define BP_APBX_CHn_CMD_CMDWORDS      12

#define BM_APBX_CHn_CMD_CMDWORDS      0x0000F000

#define BF_APBX_CHn_CMD_CMDWORDS(v)   \

	(((v) << BP_APBX_CHn_CMD_CMDWORDS) & BM_APBX_CHn_CMD_CMDWORDS)

#define BP_APBX_CHn_CMD_WAIT4ENDCMD      7

#define BM_APBX_CHn_CMD_WAIT4ENDCMD      0x00000080

#define BP_APBX_CHn_CMD_SEMAPHORE      6

#define BM_APBX_CHn_CMD_SEMAPHORE      0x00000040

#define BP_APBX_CHn_CMD_IRQONCMPLT      3

#define BM_APBX_CHn_CMD_IRQONCMPLT      0x00000008

#define BP_APBX_CHn_CMD_CHAIN      2

#define BM_APBX_CHn_CMD_CHAIN      0x00000004

#define BM_APBX_CHn_CMD_DMA_READ		0x00000003

#define BP_APBX_CHn_CMD_DMA_READ		0

#define BF_APBX_CHn_CMD_DMA_READ(v)		\

	(((v) << BP_APBX_CHn_CMD_DMA_READ) & BM_APBX_CHn_CMD_DMA_READ)

#define BP_APBX_CHn_CMD_COMMAND      0

#define BM_APBX_CHn_CMD_COMMAND      0x00000003

#define BF_APBX_CHn_CMD_COMMAND(v)   \

	(((v) << BP_APBX_CHn_CMD_COMMAND) & BM_APBX_CHn_CMD_COMMAND)

#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER  0x0

#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE    0x1

#define BV_APBX_CHn_CMD_COMMAND__DMA_READ     0x2



HW_REGISTER_RO_INDEXED(HW_APBX_CHn_BAR, REGS_APBX_BASE, 0x70, 0x70)

HW_REGISTER_0_INDEXED(HW_APBX_CHn_SEMA, REGS_APBX_BASE, 0x80, 0x70)

#define BP_APBX_CHn_SEMA_INCREMENT_SEMA      0

#define BM_APBX_CHn_SEMA_INCREMENT_SEMA      0x000000FF

#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v)   \

	(((v) << BP_APBX_CHn_SEMA_INCREMENT_SEMA) & \

	BM_APBX_CHn_SEMA_INCREMENT_SEMA)

#define BP_APBX_CHn_SEMA_PHORE      16

#define BM_APBX_CHn_SEMA_PHORE      0x00FF0000

HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG1, REGS_APBX_BASE, 0x90, 0x70)

HW_REGISTER_RO_INDEXED(HW_APBX_CHn_DEBUG2, REGS_APBX_BASE, 0xA0, 0x70)

HW_REGISTER_RO(HW_APBX_VERSION, REGS_APBX_BASE, 0x3F0)



#endif /* _INCLUDE_ASM_ARCH_REGS_APBX_H */

arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h

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#ifndef _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H

#define _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H



#include <mach/stmp3xxx_regs.h>



#define REGS_CLKCTRL_BASE (REGS_BASE + 0x00040000)



#define HW_CLKCTRL_PLLCTRL0_ADDR	(REGS_CLKCTRL_BASE + 0x00)

HW_REGISTER(HW_CLKCTRL_PLLCTRL0, REGS_CLKCTRL_BASE, 0x00)

#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS	0x00040000

#define HW_CLKCTRL_PLLCTRL1_ADDR	(REGS_CLKCTRL_BASE + 0x10)

HW_REGISTER(HW_CLKCTRL_PLLCTRL1, REGS_CLKCTRL_BASE, 0x10)



#define HW_CLKCTRL_CPU_ADDR		(REGS_CLKCTRL_BASE + 0x20)

HW_REGISTER(HW_CLKCTRL_CPU, REGS_CLKCTRL_BASE, 0x20)

#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F

#define BF_CLKCTRL_CPU_DIV_CPU(v)  \

	(((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)



#define HW_CLKCTRL_HBUS_ADDR		(REGS_CLKCTRL_BASE + 0x30)

HW_REGISTER(HW_CLKCTRL_HBUS, REGS_CLKCTRL_BASE, 0x30)

#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 	0	/* for compatitibility */

#define BM_CLKCTRL_HBUS_DIV 0x0000001F

#define BF_CLKCTRL_HBUS_DIV(v)  \

	(((v) << 0) & BM_CLKCTRL_HBUS_DIV)

#define HW_CLKCTRL_XBUS_ADDR		(REGS_CLKCTRL_BASE + 0x40)

HW_REGISTER(HW_CLKCTRL_XBUS, REGS_CLKCTRL_BASE, 0x40)

#define HW_CLKCTRL_XTAL_ADDR		(REGS_CLKCTRL_BASE + 0x50)

HW_REGISTER(HW_CLKCTRL_XTAL, REGS_CLKCTRL_BASE, 0x50)

#define HW_CLKCTRL_PIX_ADDR		(REGS_CLKCTRL_BASE + 0x60)

HW_REGISTER(HW_CLKCTRL_PIX, REGS_CLKCTRL_BASE, 0x60)

#define BM_CLKCTRL_PIX_CLKGATE		0x80000000

#define BM_CLKCTRL_PIX_BUSY		0x20000000

#define BM_CLKCTRL_PIX_DIV		0x00007FFF

#define BP_CLKCTRL_PIX_DIV		0

#define BF_CLKCTRL_PIX_DIV(v)	\

	(((v) << BP_CLKCTRL_PIX_DIV) & BM_CLKCTRL_PIX_DIV)

#define HW_CLKCTRL_SSP_ADDR		(REGS_CLKCTRL_BASE + 0x70)

HW_REGISTER(HW_CLKCTRL_SSP, REGS_CLKCTRL_BASE, 0x70)

#define HW_CLKCTRL_GPMI_ADDR		(REGS_CLKCTRL_BASE + 0x80)

HW_REGISTER(HW_CLKCTRL_GPMI, REGS_CLKCTRL_BASE, 0x80)

#define HW_CLKCTRL_SPDIF_ADDR		(REGS_CLKCTRL_BASE + 0x90)

HW_REGISTER(HW_CLKCTRL_SPDIF, REGS_CLKCTRL_BASE, 0x90)

#define HW_CLKCTRL_EMI_ADDR		(REGS_CLKCTRL_BASE + 0xA0)

HW_REGISTER(HW_CLKCTRL_EMI, REGS_CLKCTRL_BASE, 0xA0)

#define HW_CLKCTRL_IR_ADDR		(REGS_CLKCTRL_BASE + 0xB0)

HW_REGISTER(HW_CLKCTRL_IR, REGS_CLKCTRL_BASE, 0xB0)

#define HW_CLKCTRL_SAIF_ADDR		(REGS_CLKCTRL_BASE + 0xC0)

HW_REGISTER(HW_CLKCTRL_SAIF, REGS_CLKCTRL_BASE, 0xC0)

#define HW_CLKCTRL_FRAC_ADDR		(REGS_CLKCTRL_BASE + 0xD0)

HW_REGISTER(HW_CLKCTRL_FRAC, REGS_CLKCTRL_BASE, 0xD0)

#define BM_CLKCTRL_FRAC_CLKGATEIO	0x80000000

#define BM_CLKCTRL_FRAC_IO_STABLE	0x40000000

#define BM_CLKCTRL_FRAC_IOFRAC		0x3F000000

#define BP_CLKCTRL_FRAC_IOFRAC		24

#define BF_CLKCTRL_FRAC_IOFRAC(v)	\

	(((v) << BP_CLKCTRL_FRAC_IOFRAC) & BM_CLKCTRL_FRAC_IOFRAC)

#define BM_CLKCTRL_FRAC_CLKGATEPIX	0x00800000

#define BM_CLKCTRL_FRAC_PIXFRAC		0x003F0000

#define BP_CLKCTRL_FRAC_PIXFRAC		16

#define BF_CLKCTRL_FRAC_PIXFRAC(v)	\

	(((v) << BP_CLKCTRL_FRAC_PIXFRAC) & BM_CLKCTRL_FRAC_PIXFRAC)

#define BM_CLKCTRL_FRAC_CLKGATEEMI	0x00008000

#define BM_CLKCTRL_FRAC_EMIFRAC		0x00003F00

#define BP_CLKCTRL_FRAC_EMIFRAC		8

#define BF_CLKCTRL_FRAC_EMIFRAC(v)	\

	(((v) << BP_CLKCTRL_FRAC_EMIFRAC) & BM_CLKCTRL_FRAC_EMIFRAC)

#define BM_CLKCTRL_FRAC_CLKGATECPU	0x00000080

#define BM_CLKCTRL_FRAC_CPUFRAC		0x0000003F

#define BP_CLKCTRL_FRAC_CPUFRAC		0

#define BF_CLKCTRL_FRAC_CPUFRAC(v)	\

	(((v) << BP_CLKCTRL_FRAC_CPUFRAC) & BM_CLKCTRL_FRAC_CPUFRAC)

#define HW_CLKCTRL_CLKSEQ_ADDR		(REGS_CLKCTRL_BASE + 0xE0)

HW_REGISTER(HW_CLKCTRL_CLKSEQ, REGS_CLKCTRL_BASE, 0xE0)

#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU		0x00000080

#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI		0x00000040

#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP		0x00000020

#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI		0x00000010

#define BM_CLKCTRL_CLKSEQ_BYPASS_IR		0x00000008

#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX		0x00000002

#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF		0x00000001

HW_REGISTER_WO(HW_CLKCTRL_RESET, REGS_CLKCTRL_BASE, 0xF0)

#define BM_CLKCTRL_RESET_CHIP      0x00000002

#define BM_CLKCTRL_RESET_DIG	   0x00000001

#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */

arch/arm/mach-stmp37xx/include/mach/regs-icoll.h

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/*

 * Freescale STMP378X: clock registers definitions

 *

 * Embedded Alley Solutions, Inc <source@embeddedalley.com>

 *

 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.

 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.

 */



/*

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License

 * Version 2 or later at the following locations:

 *

 * http://www.opensource.org/licenses/gpl-license.html

 * http://www.gnu.org/copyleft/gpl.html

 */



#ifndef _INCLUDE_ASM_ARCH_REGS_ICOLL_H

#define _INCLUDE_ASM_ARCH_REGS_ICOLL_H





#include <mach/stmp3xxx_regs.h>



#define REGS_ICOLL_BASE (REGS_BASE + 0x00000000)



HW_REGISTER(HW_ICOLL_VECTOR, REGS_ICOLL_BASE, 0x00)

HW_REGISTER_WO(HW_ICOLL_LEVELACK, REGS_ICOLL_BASE, 0x10)

HW_REGISTER(HW_ICOLL_CTRL, REGS_ICOLL_BASE, 0x20)

#define BM_ICOLL_CTRL_CLKGATE	  0x40000000

#define BM_ICOLL_CTRL_SFTRST	   0x80000000

HW_REGISTER_RO(HW_ICOLL_STAT, REGS_ICOLL_BASE, 0x30)



HW_REGISTER_INDEXED(HW_ICOLL_PRIORITYn, REGS_ICOLL_BASE, 0x60, 0x10)



#endif /* _INCLUDE_ASM_ARCH_REGS_CLKCTRL_H */

arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h

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/*

 * STMP pinmux register definitions

 *

 * Copyright (c) 2008 Freescale Semiconductor

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 */

#ifndef _INCLUDE_ASM_ARCH_REGS_PINCTRL_H

#define _INCLUDE_ASM_ARCH_REGS_PINCTRL_H



#include <mach/stmp3xxx_regs.h>



#ifndef REGS_PINCTRL_BASE

#define REGS_PINCTRL_BASE (REGS_BASE + 0x00018000)

#endif /* REGS_PINCTRL_BASE */



HW_REGISTER(HW_PINCTRL_CTRL, REGS_PINCTRL_BASE, 0)



#define HW_PINCTRL_MUXSEL0_ADDR (REGS_PINCTRL_BASE + 0x100)

HW_REGISTER(HW_PINCTRL_MUXSEL0, REGS_PINCTRL_BASE, 0x100)

#define HW_PINCTRL_MUXSEL1_ADDR (REGS_PINCTRL_BASE + 0x110)

HW_REGISTER(HW_PINCTRL_MUXSEL1, REGS_PINCTRL_BASE, 0x110)

#define HW_PINCTRL_MUXSEL2_ADDR (REGS_PINCTRL_BASE + 0x120)

HW_REGISTER(HW_PINCTRL_MUXSEL2, REGS_PINCTRL_BASE, 0x120)

#define HW_PINCTRL_MUXSEL3_ADDR (REGS_PINCTRL_BASE + 0x130)

HW_REGISTER(HW_PINCTRL_MUXSEL3, REGS_PINCTRL_BASE, 0x130)

#define BM_PINCTRL_MUXSEL3_BANK1_PIN28      0x03000000

#define HW_PINCTRL_MUXSEL4_ADDR (REGS_PINCTRL_BASE + 0x140)

HW_REGISTER(HW_PINCTRL_MUXSEL4, REGS_PINCTRL_BASE, 0x140)

#define BM_PINCTRL_MUXSEL4_BANK2_PIN03      0x000000C0

#define BM_PINCTRL_MUXSEL4_BANK2_PIN04      0x00000300

#define HW_PINCTRL_MUXSEL5_ADDR (REGS_PINCTRL_BASE + 0x150)

HW_REGISTER(HW_PINCTRL_MUXSEL5, REGS_PINCTRL_BASE, 0x150)

#define HW_PINCTRL_MUXSEL6_ADDR (REGS_PINCTRL_BASE + 0x160)

HW_REGISTER(HW_PINCTRL_MUXSEL6, REGS_PINCTRL_BASE, 0x160)

#define HW_PINCTRL_MUXSEL7_ADDR (REGS_PINCTRL_BASE + 0x170)

HW_REGISTER(HW_PINCTRL_MUXSEL7, REGS_PINCTRL_BASE, 0x170)



HW_REGISTER(HW_PINCTRL_DRIVE0, REGS_PINCTRL_BASE, 0x200)

#define HW_PINCTRL_DRIVE0_ADDR (REGS_PINCTRL_BASE + 0x200)

HW_REGISTER(HW_PINCTRL_DRIVE1, REGS_PINCTRL_BASE, 0x210)

#define HW_PINCTRL_DRIVE1_ADDR (REGS_PINCTRL_BASE + 0x210)

HW_REGISTER(HW_PINCTRL_DRIVE2, REGS_PINCTRL_BASE, 0x220)

#define HW_PINCTRL_DRIVE2_ADDR (REGS_PINCTRL_BASE + 0x220)

HW_REGISTER(HW_PINCTRL_DRIVE3, REGS_PINCTRL_BASE, 0x230)

#define HW_PINCTRL_DRIVE3_ADDR (REGS_PINCTRL_BASE + 0x230)

HW_REGISTER(HW_PINCTRL_DRIVE4, REGS_PINCTRL_BASE, 0x240)

#define HW_PINCTRL_DRIVE4_ADDR (REGS_PINCTRL_BASE + 0x240)

HW_REGISTER(HW_PINCTRL_DRIVE5, REGS_PINCTRL_BASE, 0x250)

#define HW_PINCTRL_DRIVE5_ADDR (REGS_PINCTRL_BASE + 0x250)

HW_REGISTER(HW_PINCTRL_DRIVE6, REGS_PINCTRL_BASE, 0x260)

#define HW_PINCTRL_DRIVE6_ADDR (REGS_PINCTRL_BASE + 0x260)

HW_REGISTER(HW_PINCTRL_DRIVE7, REGS_PINCTRL_BASE, 0x270)

#define HW_PINCTRL_DRIVE7_ADDR (REGS_PINCTRL_BASE + 0x270)

HW_REGISTER(HW_PINCTRL_DRIVE8, REGS_PINCTRL_BASE, 0x280)

#define HW_PINCTRL_DRIVE8_ADDR (REGS_PINCTRL_BASE + 0x280)

HW_REGISTER(HW_PINCTRL_DRIVE9, REGS_PINCTRL_BASE, 0x290)

#define HW_PINCTRL_DRIVE9_ADDR (REGS_PINCTRL_BASE + 0x290)

HW_REGISTER(HW_PINCTRL_DRIVE10, REGS_PINCTRL_BASE, 0x2a0)

#define HW_PINCTRL_DRIVE10_ADDR (REGS_PINCTRL_BASE + 0x2a0)

HW_REGISTER(HW_PINCTRL_DRIVE11, REGS_PINCTRL_BASE, 0x2b0)

#define HW_PINCTRL_DRIVE11_ADDR (REGS_PINCTRL_BASE + 0x2b0)

HW_REGISTER(HW_PINCTRL_DRIVE12, REGS_PINCTRL_BASE, 0x2c0)

#define HW_PINCTRL_DRIVE12_ADDR (REGS_PINCTRL_BASE + 0x2c0)

HW_REGISTER(HW_PINCTRL_DRIVE13, REGS_PINCTRL_BASE, 0x2d0)

#define HW_PINCTRL_DRIVE13_ADDR (REGS_PINCTRL_BASE + 0x2d0)

HW_REGISTER(HW_PINCTRL_DRIVE14, REGS_PINCTRL_BASE, 0x2e0)

#define HW_PINCTRL_DRIVE14_ADDR (REGS_PINCTRL_BASE + 0x2e0)





HW_REGISTER(HW_PINCTRL_PULL0, REGS_PINCTRL_BASE, 0x300)

#define HW_PINCTRL_PULL0_ADDR (REGS_PINCTRL_BASE + 0x300)

#define BM_PINCTRL_PULL0_BANK0_PIN01      0x00000002

#define BM_PINCTRL_PULL0_BANK0_PIN02      0x00000004

#define BM_PINCTRL_PULL0_BANK0_PIN03      0x00000008

#define BM_PINCTRL_PULL0_BANK0_PIN04      0x00000010

#define BM_PINCTRL_PULL0_BANK0_PIN20      0x00100000

HW_REGISTER(HW_PINCTRL_PULL1, REGS_PINCTRL_BASE, 0x310)

#define HW_PINCTRL_PULL1_ADDR (REGS_PINCTRL_BASE + 0x310)

#define BM_PINCTRL_PULL1_BANK1_PIN22      0x00400000

#define BM_PINCTRL_PULL1_BANK1_PIN24      0x01000000

#define BM_PINCTRL_PULL1_BANK1_PIN25      0x02000000

#define BM_PINCTRL_PULL1_BANK1_PIN26      0x04000000

#define BM_PINCTRL_PULL1_BANK1_PIN27      0x08000000

HW_REGISTER(HW_PINCTRL_PULL2, REGS_PINCTRL_BASE, 0x320)

#define HW_PINCTRL_PULL2_ADDR (REGS_PINCTRL_BASE + 0x320)

HW_REGISTER(HW_PINCTRL_PULL3, REGS_PINCTRL_BASE, 0x330)

#define HW_PINCTRL_PULL3_ADDR (REGS_PINCTRL_BASE + 0x330)



#define HW_PINCTRL_DOUT0_ADDR (REGS_PINCTRL_BASE + 0x400)

HW_REGISTER(HW_PINCTRL_DOUT0, REGS_PINCTRL_BASE, 0x400)

#define HW_PINCTRL_DOUT1_ADDR (REGS_PINCTRL_BASE + 0x410)

HW_REGISTER(HW_PINCTRL_DOUT1, REGS_PINCTRL_BASE, 0x410)

#define HW_PINCTRL_DOUT2_ADDR (REGS_PINCTRL_BASE + 0x420)

HW_REGISTER(HW_PINCTRL_DOUT2, REGS_PINCTRL_BASE, 0x420)



#define HW_PINCTRL_DIN0_ADDR (REGS_PINCTRL_BASE + 0x500)

HW_REGISTER_RO(HW_PINCTRL_DIN0, REGS_PINCTRL_BASE, 0x500)

#define HW_PINCTRL_DIN1_ADDR (REGS_PINCTRL_BASE + 0x510)

HW_REGISTER_RO(HW_PINCTRL_DIN1, REGS_PINCTRL_BASE, 0x510)

#define HW_PINCTRL_DIN2_ADDR (REGS_PINCTRL_BASE + 0x520)

HW_REGISTER_RO(HW_PINCTRL_DIN2, REGS_PINCTRL_BASE, 0x520)



#define HW_PINCTRL_DOE0_ADDR (REGS_PINCTRL_BASE + 0x600)

HW_REGISTER(HW_PINCTRL_DOE0, REGS_PINCTRL_BASE, 0x600)

#define HW_PINCTRL_DOE1_ADDR (REGS_PINCTRL_BASE + 0x610)

HW_REGISTER(HW_PINCTRL_DOE1, REGS_PINCTRL_BASE, 0x610)

#define HW_PINCTRL_DOE2_ADDR (REGS_PINCTRL_BASE + 0x620)

HW_REGISTER(HW_PINCTRL_DOE2, REGS_PINCTRL_BASE, 0x620)



HW_REGISTER(HW_PINCTRL_PIN2IRQ0, REGS_PINCTRL_BASE, 0x700)

#define HW_PINCTRL_PIN2IRQ0_ADDR (REGS_PINCTRL_BASE + 0x700)

HW_REGISTER(HW_PINCTRL_PIN2IRQ1, REGS_PINCTRL_BASE, 0x710)

#define HW_PINCTRL_PIN2IRQ1_ADDR (REGS_PINCTRL_BASE + 0x710)

HW_REGISTER(HW_PINCTRL_PIN2IRQ2, REGS_PINCTRL_BASE, 0x720)

#define HW_PINCTRL_PIN2IRQ2_ADDR (REGS_PINCTRL_BASE + 0x720)



HW_REGISTER(HW_PINCTRL_IRQEN0, REGS_PINCTRL_BASE, 0x800)

#define HW_PINCTRL_IRQEN0_ADDR (REGS_PINCTRL_BASE + 0x800)

HW_REGISTER(HW_PINCTRL_IRQEN1, REGS_PINCTRL_BASE, 0x810)

#define HW_PINCTRL_IRQEN1_ADDR (REGS_PINCTRL_BASE + 0x810)

HW_REGISTER(HW_PINCTRL_IRQEN2, REGS_PINCTRL_BASE, 0x820)

#define HW_PINCTRL_IRQEN2_ADDR (REGS_PINCTRL_BASE + 0x820)



HW_REGISTER(HW_PINCTRL_IRQLEVEL0, REGS_PINCTRL_BASE, 0x900)

#define HW_PINCTRL_IRQLEVEL0_ADDR (REGS_PINCTRL_BASE + 0x900)

HW_REGISTER(HW_PINCTRL_IRQLEVEL1, REGS_PINCTRL_BASE, 0x910)

#define HW_PINCTRL_IRQLEVEL1_ADDR (REGS_PINCTRL_BASE + 0x910)

HW_REGISTER(HW_PINCTRL_IRQLEVEL2, REGS_PINCTRL_BASE, 0x920)

#define HW_PINCTRL_IRQLEVEL2_ADDR (REGS_PINCTRL_BASE + 0x920)



HW_REGISTER(HW_PINCTRL_IRQPOL0, REGS_PINCTRL_BASE, 0xA00)

#define HW_PINCTRL_IRQPOL0_ADDR (REGS_PINCTRL_BASE + 0xa00)

HW_REGISTER(HW_PINCTRL_IRQPOL1, REGS_PINCTRL_BASE, 0xA10)

#define HW_PINCTRL_IRQPOL1_ADDR (REGS_PINCTRL_BASE + 0xa10)

HW_REGISTER(HW_PINCTRL_IRQPOL2, REGS_PINCTRL_BASE, 0xA20)

#define HW_PINCTRL_IRQPOL2_ADDR (REGS_PINCTRL_BASE + 0xa20)



HW_REGISTER(HW_PINCTRL_IRQSTAT0, REGS_PINCTRL_BASE, 0xB00)

#define HW_PINCTRL_IRQSTAT0_ADDR (REGS_PINCTRL_BASE + 0xb00)

HW_REGISTER(HW_PINCTRL_IRQSTAT1, REGS_PINCTRL_BASE, 0xB10)

#define HW_PINCTRL_IRQSTAT1_ADDR (REGS_PINCTRL_BASE + 0xb10)

HW_REGISTER(HW_PINCTRL_IRQSTAT2, REGS_PINCTRL_BASE, 0xB20)

#define HW_PINCTRL_IRQSTAT2_ADDR (REGS_PINCTRL_BASE + 0xb20)



#endif /* _INCLUDE_ASM_ARCH_REGS_PINCTRL_H */