Loading drivers/clk/qcom/mdss/mdss-hdmi-pll-8998.c +1 −1 Original line number Diff line number Diff line Loading @@ -82,7 +82,7 @@ #define HDMI_HZ_TO_MHZ 1000000 #define HDMI_REF_CLOCK_MHZ 19.2 #define HDMI_REF_CLOCK_HZ (HDMI_REF_CLOCK_MHZ * 1000000) #define HDMI_VCO_MIN_RATE_HZ 30000000 #define HDMI_VCO_MIN_RATE_HZ 25000000 #define HDMI_VCO_MAX_RATE_HZ 600000000 struct 8998_reg_cfg { Loading Loading
drivers/clk/qcom/mdss/mdss-hdmi-pll-8998.c +1 −1 Original line number Diff line number Diff line Loading @@ -82,7 +82,7 @@ #define HDMI_HZ_TO_MHZ 1000000 #define HDMI_REF_CLOCK_MHZ 19.2 #define HDMI_REF_CLOCK_HZ (HDMI_REF_CLOCK_MHZ * 1000000) #define HDMI_VCO_MIN_RATE_HZ 30000000 #define HDMI_VCO_MIN_RATE_HZ 25000000 #define HDMI_VCO_MAX_RATE_HZ 600000000 struct 8998_reg_cfg { Loading