Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 34494fcf authored by Suresh Vankadara's avatar Suresh Vankadara
Browse files

msm: camera: icp: Dynamic clock bandwidth support 



Add support for IPE and BPS dynamic clock
and bandwidth for realtime streams. Add support
to set clock and bandwidth based on user request
for debug purpose. Following command is used to
provide clock rate from user.

echo "clk rate" > /sys/kernel/debug/camera_icp/icp_debug_clk

Change-Id: I9a2cfefc8227190cd79257d948d37127767e50e1
Signed-off-by: default avatarSuresh Vankadara <svankada@codeaurora.org>
parent fd4a1668

Documentation/devicetree/bindings/media/video/msm-cam-icp.txt

+30 −7
Original line number Diff line number Diff line
@@ -105,6 +105,11 @@ and name of firmware image. 
  Value type: <string>

  Definition: List of clock names required for CDM HW.



- src-clock-name

  Usage: required

  Value type: <string>

  Definition: Source clock name.



- clocks

  Usage: required

  Value type: <phandle>
@@ -114,7 +119,7 @@ and name of firmware image. 
  Usage: required

  Value type: <string>

  Definition: List of strings corresponds clock-rates levels.

  Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo.

  Supported strings: lowsvs, svs, svs_l1, nominal, turbo.



- clock-rates

  Usage: required
@@ -176,14 +181,20 @@ qcom,ipe0 { 
		"ipe_0_axi_clk",

		"ipe_0_clk",

		"ipe_0_clk_src";

	src-clock-name = "ipe_0_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK>,

			<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 240000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 538000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};



qcom,ipe1 {
@@ -196,14 +207,20 @@ qcom,ipe1 { 
		"ipe_1_axi_clk",

		"ipe_1_clk",

		"ipe_1_clk_src";

	src-clock-name = "ipe_1_clk_src";

	clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

			<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK>,

			<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 240000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 538000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};



bps: qcom,bps {
@@ -216,13 +233,19 @@ bps: qcom,bps { 
		"bps_axi_clk",

		"bps_clk",

		"bps_clk_src";

	src-clock-name = "bps_clk_src";

	clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

			<&clock_camcc CAM_CC_BPS_AREG_CLK>,

			<&clock_camcc CAM_CC_BPS_AXI_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK>,

			<&clock_camcc CAM_CC_BPS_CLK_SRC>;



	clock-rates = <80000000 400000000 0 0 600000000>;

	clock-cntl-level = "turbo";

	clock-rates = <0 0 0 0 200000000>,

		<0 0 0 0 404000000>,

		<0 0 0 0 480000000>,

		<0 0 0 0 600000000>,

		<0 0 0 0 600000000>;

	clock-cntl-level = "lowsvs", "svs",

		"svs_l1", "nominal", "turbo";

};

arch/arm64/boot/dts/qcom/sdm845-camera.dtsi

+24 −6
Original line number Diff line number Diff line
@@ -840,14 +840,20 @@ 
			"ipe_0_axi_clk",

			"ipe_0_clk",

			"ipe_0_clk_src";

		src-clock-name = "ipe_0_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_0_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK>,

				<&clock_camcc CAM_CC_IPE_0_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 240000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 538000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};
@@ -861,14 +867,20 @@ 
			"ipe_1_axi_clk",

			"ipe_1_clk",

			"ipe_1_clk_src";

		src-clock-name = "ipe_1_clk_src";

		clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AREG_CLK>,

				<&clock_camcc CAM_CC_IPE_1_AXI_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK>,

				<&clock_camcc CAM_CC_IPE_1_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 240000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 538000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};
@@ -882,14 +894,20 @@ 
			"bps_axi_clk",

			"bps_clk",

			"bps_clk_src";

		src-clock-name = "bps_clk_src";

		clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,

				<&clock_camcc CAM_CC_BPS_AREG_CLK>,

				<&clock_camcc CAM_CC_BPS_AXI_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK>,

				<&clock_camcc CAM_CC_BPS_CLK_SRC>;



		clock-rates = <0 0 0 0 600000000>;

		clock-cntl-level = "turbo";

		clock-rates = <0 0 0 0 200000000>,

			<0 0 0 0 404000000>,

			<0 0 0 0 480000000>,

			<0 0 0 0 600000000>,

			<0 0 0 0 600000000>;

		clock-cntl-level = "lowsvs", "svs",

			"svs_l1", "nominal", "turbo";

		status = "ok";

	};

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_core.c

+9 −2
Original line number Diff line number Diff line
@@ -75,8 +75,8 @@ int cam_bps_init_hw(void *device_priv, 


	cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE;

	cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE;

	cpas_vote.axi_vote.compressed_bw = ICP_TURBO_VOTE;

	cpas_vote.axi_vote.uncompressed_bw = ICP_TURBO_VOTE;

	cpas_vote.axi_vote.compressed_bw = CAM_CPAS_DEFAULT_AXI_BW;

	cpas_vote.axi_vote.uncompressed_bw = CAM_CPAS_DEFAULT_AXI_BW;



	rc = cam_cpas_start(core_info->cpas_handle,

			&cpas_vote.ahb_vote, &cpas_vote.axi_vote);
@@ -269,6 +269,13 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, 
	case CAM_ICP_BPS_CMD_POWER_RESUME:

		rc = cam_bps_handle_resume(bps_dev);

		break;

	case CAM_ICP_BPS_CMD_UPDATE_CLK: {

		uint32_t clk_rate = *(uint32_t *)cmd_args;



		CAM_DBG(CAM_ICP, "bps_src_clk rate = %d", (int)clk_rate);

		rc = cam_bps_update_clk_rate(soc_info, clk_rate);

	}

		break;

	default:

		break;

	}

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_soc.c

+10 −0
Original line number Diff line number Diff line
@@ -132,3 +132,13 @@ int cam_bps_get_gdsc_control(struct cam_hw_soc_info *soc_info) 


	return rc;

}



int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info,

	uint32_t clk_rate)

{

	if (!soc_info)

		return -EINVAL;



	return cam_soc_util_set_clk_rate(soc_info->clk[soc_info->src_clk_idx],

		soc_info->clk_name[soc_info->src_clk_idx], clk_rate);

}

drivers/media/platform/msm/camera/cam_icp/icp_hw/bps_hw/bps_soc.h

+2 −0
Original line number Diff line number Diff line
@@ -26,4 +26,6 @@ int cam_bps_get_gdsc_control(struct cam_hw_soc_info *soc_info); 


int cam_bps_transfer_gdsc_control(struct cam_hw_soc_info *soc_info);



int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info,

	uint32_t clk_rate);

#endif /* _CAM_BPS_SOC_H_*/