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Commit 343f1327 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Linus Walleij
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pinctrl: sunxi: number gpio ranges starting from 0 



The pinctrl-sunxi driver originally used the pin number as the gpio
range offset. This resulted in large, bogus gpio numbers for the
new sun6i-a31-r pinctrl devices.

This patch makes the driver number the gpios ranges starting from an
offset of 0, by subtracting the pin_base number from the pin number.
This also makes the system-wide gpio number match the pin number.

Tested on sun8i with sysfs exported gpios.

This patch also changes the GPIO bindings for R_PIO:

    gpios = <&r_pio B N flag>;

Where B originally was the pinbank label (L or M) counted from A,
with this patch it becomes (L or M) counted from its pinbank base (L).

Thus

    gpios = <&r_pio 10 11 0>; /* PL11 */

becomes

    gpios = <&r_pio 0 11 0>; /* PL11 */

IMO this is correct, as the binding shows the bank offset and pin offset
within the bank for the GPIO controller. But I'm worried it might be a
bit confusing.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent f83549d6

drivers/pinctrl/sunxi/pinctrl-sunxi.c

+8 −5
Original line number Original line Diff line number Diff line
@@ -507,7 +507,7 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 
	base = PINS_PER_BANK * gpiospec->args[0];

	base = PINS_PER_BANK * gpiospec->args[0];

	pin = base + gpiospec->args[1];

	pin = base + gpiospec->args[1];





	if (pin > (gc->base + gc->ngpio))

	if (pin > gc->ngpio)

		return -EINVAL;

		return -EINVAL;





	if (flags)

	if (flags)
@@ -520,12 +520,13 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 
{

{

	struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);

	struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);

	struct sunxi_desc_function *desc;

	struct sunxi_desc_function *desc;

	unsigned pinnum = pctl->desc->pin_base + offset;

	unsigned irqnum;

	unsigned irqnum;





	if (offset >= chip->ngpio)

	if (offset >= chip->ngpio)

		return -ENXIO;

		return -ENXIO;





	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");

	desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");

	if (!desc)

	if (!desc)

		return -EINVAL;

		return -EINVAL;
@@ -548,7 +549,8 @@ static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 
	if (!func)

	if (!func)

		return -EINVAL;

		return -EINVAL;





	ret = gpio_lock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]);

	ret = gpio_lock_as_irq(pctl->chip,

			pctl->irq_array[d->hwirq] - pctl->desc->pin_base);

	if (ret) {

	if (ret) {

		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",

		dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",

			irqd_to_hwirq(d));

			irqd_to_hwirq(d));
@@ -565,7 +567,8 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 
{

{

	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);

	struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);





	gpio_unlock_as_irq(pctl->chip, pctl->irq_array[d->hwirq]);

	gpio_unlock_as_irq(pctl->chip,

			   pctl->irq_array[d->hwirq] - pctl->desc->pin_base);

}

}





static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)

static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
@@ -931,7 +934,7 @@ int sunxi_pinctrl_init(struct platform_device *pdev, 
		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;

		const struct sunxi_desc_pin *pin = pctl->desc->pins + i;





		ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),

		ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),

					     pin->pin.number,

					     pin->pin.number - pctl->desc->pin_base,

					     pin->pin.number, 1);

					     pin->pin.number, 1);

		if (ret)

		if (ret)

			goto gpiochip_error;

			goto gpiochip_error;