Merge "clk: qcom: gcc-sdxpoorwills: add USB/PCIe reference clocks" (34059dfb) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/gcc-sdxpoorwills.c

+32 −3

Original line number	Diff line number	Diff line
		@@ -1353,6 +1353,19 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
		},
		};

		static struct clk_branch gcc_pcie_0_clkref_clk = {
		.halt_reg = 0x88004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x88004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_pcie_aux_clk = {
		.halt_reg = 0x37020,
		.halt_check = BRANCH_HALT_VOTED,
		@@ -1695,14 +1708,26 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
		},
		};

		static struct clk_branch gcc_usb3_phy_pipe_clk = {
		.halt_reg = 0xb054,
		.halt_check = BRANCH_HALT,
		static struct clk_gate2 gcc_usb3_phy_pipe_clk = {
		.udelay = 500,
		.clkr = {
		.enable_reg = 0xb054,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_phy_pipe_clk",
		.ops = &clk_gate2_ops,
		},
		},
		};

		static struct clk_branch gcc_usb3_prim_clkref_clk = {
		.halt_reg = 0x88000,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x88000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_prim_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1782,6 +1807,7 @@ static struct clk_regmap *gcc_sdxpoorwills_clocks[] = {
		[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
		[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
		[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
		[GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
		[GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
		[GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
		[GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
		@@ -1813,6 +1839,7 @@ static struct clk_regmap *gcc_sdxpoorwills_clocks[] = {
		[GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
		[GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
		[GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
		[GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
		[GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
		[GPLL0] = &gpll0.clkr,
		[GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
		@@ -1837,6 +1864,8 @@ static const struct qcom_reset_map gcc_sdxpoorwills_resets[] = {
		[GCC_SDCC1_BCR] = { 0xf000 },
		[GCC_SPMI_FETCHER_BCR] = { 0x3f000 },
		[GCC_USB30_BCR] = { 0xb000 },
		[GCC_USB3_PHY_BCR] = { 0xc000 },
		[GCC_USB3PHY_PHY_BCR] = { 0xc004 },
		[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
		};

include/dt-bindings/clock/qcom,gcc-sdxpoorwills.h

+38 −37

Original line number	Diff line number	Diff line
		@@ -65,43 +65,44 @@
		#define GCC_MSS_CFG_AHB_CLK 47
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 48
		#define GCC_MSS_SNOC_AXI_CLK 49
		#define GCC_PCIE_AUX_CLK 50
		#define GCC_PCIE_AUX_PHY_CLK_SRC 51
		#define GCC_PCIE_CFG_AHB_CLK 52
		#define GCC_PCIE_MSTR_AXI_CLK 53
		#define GCC_PCIE_PHY_REFGEN_CLK 54
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 55
		#define GCC_PCIE_PIPE_CLK 56
		#define GCC_PCIE_SLEEP_CLK 57
		#define GCC_PCIE_SLV_AXI_CLK 58
		#define GCC_PCIE_SLV_Q2A_AXI_CLK 59
		#define GCC_PDM2_CLK 60
		#define GCC_PDM2_CLK_SRC 61
		#define GCC_PDM_AHB_CLK 62
		#define GCC_PDM_XO4_CLK 63
		#define GCC_PRNG_AHB_CLK 64
		#define GCC_SDCC1_AHB_CLK 65
		#define GCC_SDCC1_APPS_CLK 66
		#define GCC_SDCC1_APPS_CLK_SRC 67
		#define GCC_SPMI_FETCHER_AHB_CLK 68
		#define GCC_SPMI_FETCHER_CLK 69
		#define GCC_SPMI_FETCHER_CLK_SRC 70
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 71
		#define GCC_SYS_NOC_USB3_CLK 72
		#define GCC_USB30_MASTER_CLK 73
		#define GCC_USB30_MASTER_CLK_SRC 74
		#define GCC_USB30_MOCK_UTMI_CLK 75
		#define GCC_USB30_MOCK_UTMI_CLK_SRC 76
		#define GCC_USB30_SLEEP_CLK 77
		#define GCC_USB3_PHY_AUX_CLK 78
		#define GCC_USB3_PHY_AUX_CLK_SRC 79
		#define GCC_USB3_PHY_PIPE_CLK 80
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 81
		#define GPLL0 82
		#define GPLL0_OUT_EVEN 83
		#define GPLL4 84
		#define GPLL4_OUT_EVEN 85
		#define GCC_USB3_PRIM_CLKREF_CLK 86
		#define GCC_PCIE_0_CLKREF_CLK 50
		#define GCC_PCIE_AUX_CLK 51
		#define GCC_PCIE_AUX_PHY_CLK_SRC 52
		#define GCC_PCIE_CFG_AHB_CLK 53
		#define GCC_PCIE_MSTR_AXI_CLK 54
		#define GCC_PCIE_PHY_REFGEN_CLK 55
		#define GCC_PCIE_PHY_REFGEN_CLK_SRC 56
		#define GCC_PCIE_PIPE_CLK 57
		#define GCC_PCIE_SLEEP_CLK 58
		#define GCC_PCIE_SLV_AXI_CLK 59
		#define GCC_PCIE_SLV_Q2A_AXI_CLK 60
		#define GCC_PDM2_CLK 61
		#define GCC_PDM2_CLK_SRC 62
		#define GCC_PDM_AHB_CLK 63
		#define GCC_PDM_XO4_CLK 64
		#define GCC_PRNG_AHB_CLK 65
		#define GCC_SDCC1_AHB_CLK 66
		#define GCC_SDCC1_APPS_CLK 67
		#define GCC_SDCC1_APPS_CLK_SRC 68
		#define GCC_SPMI_FETCHER_AHB_CLK 69
		#define GCC_SPMI_FETCHER_CLK 70
		#define GCC_SPMI_FETCHER_CLK_SRC 71
		#define GCC_SYS_NOC_CPUSS_AHB_CLK 72
		#define GCC_SYS_NOC_USB3_CLK 73
		#define GCC_USB30_MASTER_CLK 74
		#define GCC_USB30_MASTER_CLK_SRC 75
		#define GCC_USB30_MOCK_UTMI_CLK 76
		#define GCC_USB30_MOCK_UTMI_CLK_SRC 77
		#define GCC_USB30_SLEEP_CLK 78
		#define GCC_USB3_PHY_AUX_CLK 79
		#define GCC_USB3_PHY_AUX_CLK_SRC 80
		#define GCC_USB3_PHY_PIPE_CLK 81
		#define GCC_USB3_PRIM_CLKREF_CLK 82
		#define GCC_USB_PHY_CFG_AHB2PHY_CLK 83
		#define GPLL0 84
		#define GPLL0_OUT_EVEN 85
		#define GPLL4 86
		#define GPLL4_OUT_EVEN 87

		/* CPU clocks */
		#define CLOCK_A7SS 0