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Commit 33d9e9b5 authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
Browse files

[PATCH] ppc32: Add support for Freescale e200 (Book-E) core 



The e200 core is a Book-E core (similar to e500) that has a unified L1 cache
and is not cache coherent on the bus.  The e200 core also adds a separate
exception level for debug exceptions.  Part of this patch helps to cleanup a
few cases that are true for all Freescale Book-E parts, not just e500.

Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 62aa751d

arch/ppc/Kconfig

+10 −7
Original line number Diff line number Diff line
@@ -88,6 +88,9 @@ config 8xx 
	depends on BROKEN

	bool "8xx"



config E200

	bool "e200"



config E500

	bool "e500"
@@ -98,12 +101,12 @@ config PPC_FPU 


config BOOKE

	bool

	depends on E500

	depends on E200 || E500

	default y



config FSL_BOOKE

	bool

	depends on E500

	depends on E200 || E500

	default y



config PTE_64BIT
@@ -141,16 +144,16 @@ config ALTIVEC 


config SPE

	bool "SPE Support"

	depends on E500

	depends on E200 || E500

	---help---

	  This option enables kernel support for the Signal Processing

	  Extensions (SPE) to the PowerPC processor. The kernel currently

	  supports saving and restoring SPE registers, and turning on the

	  'spe enable' bit so user processes can execute SPE instructions.



	  This option is only usefully if you have a processor that supports

	  This option is only useful if you have a processor that supports

	  SPE (e500, otherwise known as 85xx series), but does not have any

	  affect on a non-spe cpu (it does, however add code to the kernel).

	  effect on a non-spe cpu (it does, however add code to the kernel).



	  If in doubt, say Y here.
@@ -200,7 +203,7 @@ config TAU_AVERAGE 


config MATH_EMULATION

	bool "Math emulation"

	depends on 4xx || 8xx || E500

	depends on 4xx || 8xx || E200 || E500

	---help---

	  Some PowerPC chips designed for embedded applications do not have

	  a floating-point unit and therefore do not implement the
@@ -254,7 +257,7 @@ config PPC_STD_MMU 


config NOT_COHERENT_CACHE

	bool

	depends on 4xx || 8xx

	depends on 4xx || 8xx || E200

	default y



endmenu

arch/ppc/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ CPP = $(CC) -E $(CFLAGS) 


CHECKFLAGS	+= -D__powerpc__



ifndef CONFIG_E500

ifndef CONFIG_FSL_BOOKE

CFLAGS		+= -mstring

endif
@@ -38,6 +38,7 @@ cpu-as-$(CONFIG_4xx) += -Wa,-m405 
cpu-as-$(CONFIG_6xx)		+= -Wa,-maltivec

cpu-as-$(CONFIG_POWER4)		+= -Wa,-maltivec

cpu-as-$(CONFIG_E500)		+= -Wa,-me500

cpu-as-$(CONFIG_E200)		+= -Wa,-me200



AFLAGS += $(cpu-as-y)

CFLAGS += $(cpu-as-y)

arch/ppc/kernel/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -26,7 +26,9 @@ obj-$(CONFIG_KGDB) += ppc-stub.o 
obj-$(CONFIG_SMP)		+= smp.o smp-tbsync.o

obj-$(CONFIG_TAU)		+= temp.o

obj-$(CONFIG_ALTIVEC)		+= vecemu.o vector.o

ifndef CONFIG_E200

obj-$(CONFIG_FSL_BOOKE)		+= perfmon_fsl_booke.o

endif



ifndef CONFIG_MATH_EMULATION

obj-$(CONFIG_8xx)		+= softemu8xx.o

arch/ppc/kernel/cputable.c

+24 −1
Original line number Diff line number Diff line
@@ -903,7 +903,30 @@ struct cpu_spec cpu_specs[] = { 
		.dcache_bsize		= 32,

	},

#endif /* CONFIG_44x */

#ifdef CONFIG_E500

#ifdef CONFIG_FSL_BOOKE

	{ 	/* e200z5 */

		.pvr_mask		= 0xfff00000,

		.pvr_value		= 0x81000000,

		.cpu_name		= "e200z5",

		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */

		.cpu_features		= CPU_FTR_USE_TB,

		.cpu_user_features	= PPC_FEATURE_32 |

			PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |

			PPC_FEATURE_UNIFIED_CACHE,

		.dcache_bsize		= 32,

	},

	{ 	/* e200z6 */

		.pvr_mask		= 0xfff00000,

		.pvr_value		= 0x81100000,

		.cpu_name		= "e200z6",

		/* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */

		.cpu_features		= CPU_FTR_USE_TB,

		.cpu_user_features	= PPC_FEATURE_32 |

			PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |

			PPC_FEATURE_HAS_EFP_SINGLE |

			PPC_FEATURE_UNIFIED_CACHE,

		.dcache_bsize		= 32,

	},

	{ 	/* e500 */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80200000,

arch/ppc/kernel/entry.S

+9 −0
Original line number Diff line number Diff line
@@ -60,6 +60,11 @@ mcheck_transfer_to_handler: 
	TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK)

	b	transfer_to_handler_full



	.globl	debug_transfer_to_handler

debug_transfer_to_handler:

	TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG)

	b	transfer_to_handler_full



	.globl	crit_transfer_to_handler

crit_transfer_to_handler:

	TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT)
@@ -835,6 +840,10 @@ ret_from_crit_exc: 
	RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI)



#ifdef CONFIG_BOOKE

	.globl	ret_from_debug_exc

ret_from_debug_exc:

	RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI)



	.globl	ret_from_mcheck_exc

ret_from_mcheck_exc:

	RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI)